--Quad 2-input Nand--Simple concurrent model of a TTL quad nand gate.--uses 1993 std VHDLlibrary IEEE;use IEEE.Std_logic_1164.all;entity HCT00 isport(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;Y1, Y2, Y3, Y4 : out std_logic);end HCT00;architecture VER1 of HCT00 isbeginY1 <= A1 nand B1 after 10 ns;Y2 <= A2 nand B2 after 10 ns;Y3 <= A3 nand B3 after 10 ns;Y4 <= A4 nand B4 after 10 ns;end VER1;