--Behavioural description of an 8-bit Shift Register--8-bit universal shift register modelled using a processENTITY shftreg8 ISPORT(clock, serinl, serinr : IN BIT; --clock and serial inputsmode : IN BIT_VECTOR(0 TO 1);--"00" : disabled; "10" : shift left; "01" : shift right; "11" : Parallelload;parin : IN BIT_VECTOR(0 TO 7); --parallel inputsparout : OUT BIT_VECTOR(0 TO 7)); --parallel outputsEND shftreg8;ARCHITECTURE behavioural OF shftreg8 ISBEGINPROCESS--declare variable to hold register stateVARIABLE state : BIT_VECTOR(0 TO 7) := "00000000";BEGIN--synchronise process to rising edges of clockWAIT UNTIL clock'EVENT AND clock = '1';CASE mode ISWHEN "00" => state := state; --disabledWHEN "10" =>FOR i IN 0 TO 7 LOOP --shiftleftIF i = 7 THENstate(i) := serinl;ELSEstate(i) := state(i + 1);END IF;END LOOP;WHEN "01" =>FOR i IN 7 DOWNTO 0 LOOP --shiftrightIF i = 0 THENstate(i) := serinr;ELSEstate(i) := state(i - 1);END IF;END LOOP;WHEN "11" => state := parin; --parallelloadEND CASE;--assign variable to parallel output portparout <= state;END PROCESS;END behavioural;