library IEEE;
use IEEE.std_logic_1164.all;

--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;




--This package is a version of the Synopsys package and has been 
-- optimized for use with the Express compiler.
library SYNOPSYS;
use SYNOPSYS.attributes.all;




entity PULSE2 is
    port (
        CLKR: in STD_LOGIC;
        CLKL: in STD_LOGIC;
        LED:out STD_LOGIC_VECTOR(7 DOWNTO 0);
        SWOUT:out STD_LOGIC_VECTOR(7 DOWNTO 0)

    );
end PULSE2;

architecture PULSE2_arch of PULSE2 is

component OS
   port (OSout:out std_logic);
end component ;


SIGNAL COUNT2,COUNT3,COUNT4,COUNT5,COUNT6,COUNT7:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER7:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL COUNTER6:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL COUNTT,COUNT1,COUNTR:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK1,CLK2,CLK3,CLK4,CLK5,CLK6,CLK7,FLAG,FLAGR,OUTL,OUTR:STD_LOGIC;

begin
  -- <<enter your statements here>>
  U1:OS PORT MAP(CLK7);
  
  P9:PROCESS(CLK7,COUNT3)
  BEGIN
  IF(CLK7='1' AND CLK7'EVENT)THEN
     COUNT3<=COUNT3+1;
  END IF;
  END PROCESS;
  CLK6<=COUNT3(3);
  
  
  P8:PROCESS(CLK6,COUNT4)
  BEGIN
  IF(CLK6='1' AND CLK6'EVENT)THEN
     COUNT4<=COUNT4+1;
  END IF;
  END PROCESS;
  CLK5<=COUNT4(3);
  
  P0:PROCESS(CLK5,COUNT1)
  BEGIN
  IF(CLK5='1' AND CLK5'EVENT)THEN
     COUNT1<=COUNT1+1;
  END IF;
  END PROCESS;
  CLK2<=COUNT1(3);
  
  P1:PROCESS(CLK2,COUNTER7)
  BEGIN
  IF(CLK2='1' AND CLK2'EVENT)THEN
    COUNTER7<=COUNTER7+1;
  END IF;
  END PROCESS;
  CLK3<=COUNTER7(6);
  SWOUT(5 DOWNTO 0)<=COUNTER7(5 DOWNTO 0);
  CLK4<=COUNTER7(7);
  P2:PROCESS(CLK3,COUNTER6)
  BEGIN
  IF(CLK3='1' AND CLK3'EVENT)THEN
     COUNTER6<=COUNTER6+1;
  END IF;
  END PROCESS;
    LED(5 DOWNTO 0)<=NOT COUNTER6;

     

  P4:PROCESS(CLK2,CLKL,CLKR,COUNT5,COUNT6)
  BEGIN
  IF(CLK2='1' AND CLK2'EVENT)THEN
       IF(COUNT5<7)THEN
       	  IF(CLKL='1')THEN
       	     COUNT5<=COUNT5+1;
      	  ELSE
             COUNT5<="0000";
       	  END IF;
       	  OUTL<='0';
       ELSIF(COUNT5<15)THEN
          IF(CLKL='1')THEN
             COUNT5<="1000";
          ELSE
             COUNT5<=COUNT5+1;
          END IF;
          OUTL<='1';
      ELSE
          COUNT5<="0000";
          OUTL<='0';
      END IF;     
                
       IF(COUNT6<7)THEN
       	  IF(CLKR='1')THEN
       	     COUNT6<=COUNT6+1;
      	  ELSE
             COUNT6<="0000";
       	  END IF;
       	  OUTR<='0';
       ELSIF(COUNT6<15)THEN
          IF(CLKR='1')THEN
             COUNT6<="1000";
          ELSE
             COUNT6<=COUNT6+1;
          END IF;
          OUTR<='1';
      ELSE
          COUNT6<="0000";
          OUTR<='1';
      END IF;    
  
  END IF;
  END PROCESS;
  
  LED(6)<=NOT OUTL;
  LED(7)<=NOT OUTR;
  
  
  P12:PROCESS(CLK4,OUTR,COUNTT,COUNTR)
  BEGIN
  IF(CLK4='1' AND CLK4'EVENT)THEN
     IF(COUNTT=0 )THEN
          IF(OUTL='1')THEN COUNTT<=COUNTT+1;
          ELSE COUNTT<=COUNTT;END IF;
          FLAG<='0';
          
      ELSIF(COUNTT<31)THEN
          COUNTT<=COUNTT+1;
          FLAG<='1';
      ELSIF(COUNTT=31)THEN
        IF(OUTL='0')THEN
          COUNTT<="00000";
        ELSE 
          COUNTT<=COUNTT;
        END IF;
        FLAG<='0';
      END IF;
      
      IF(COUNTR=0 )THEN
          IF(OUTR='1')THEN COUNTR<=COUNTR+1;
          ELSE COUNTR<=COUNTR;END IF;
          FLAGR<='0';
          
      ELSIF(COUNTR<10)THEN
          COUNTR<=COUNTR+1;
          FLAGR<='1';
      ELSE
        IF(OUTL='0')THEN
          COUNTR<="00000";
        ELSE 
          COUNTR<=COUNTR;
        END IF;
      END IF;
      
   END IF;
  END PROCESS;
     
   
  SWOUT(6)<=CLK4 AND FLAGR; 
  SWOUT(7)<=CLK4 AND FLAG;
  
end PULSE2_arch;