LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY pwide IS    PORT (		CLK : IN STD_LOGIC;        A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);		PSOUT : OUT STD_LOGIC	);END pwide;ARCHITECTURE mixed OF pwide ISCOMPONENT CNT8    PORT (        CLK, LD : IN STD_LOGIC;        D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);        CAO : OUT STD_LOGIC    );END COMPONENT;    SIGNAL CAO1, CAO2 : STD_LOGIC;    SIGNAL LD1, LD2 : STD_LOGIC;	SIGNAL PSINT : STD_LOGIC;BEGIN    U1 : CNT8	PORT MAP(	    CLK => CLK,		LD => LD1,		D => A,        CAO => CAO1	);    U2 : CNT8	PORT MAP(	    CLK => CLK,		LD => LD2,		D => B,        CAO => CAO2	);	PROCESS(CAO1, CAO2)	BEGIN        IF CAO2 = '1' THEN		    PSINT <= '0';		ELSIF CAO1'EVENT AND CAO1 = '1' THEN		    PSINT <= '1';	    END IF;	END PROCESS;	LD1 <= PSINT;	LD2 <= NOT PSINT;	PSOUT <= PSINT;END mixed;