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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component counter
	port (
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic;
	UP: IN std_logic;
	LOAD: IN std_logic;
	L: IN std_logic_VECTOR(15 downto 0);
	CE: IN std_logic;
	ACLR: IN std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of counter: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of counter: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : counter
		port map (
			Q => Q,
			CLK => CLK,
			UP => UP,
			LOAD => LOAD,
			L => L,
			CE => CE,
			ACLR => ACLR);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file counter.vhd when simulating
-- the core, counter. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".