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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file counter.v when simulating
// the core, counter. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module counter(
	Q,
	CLK,
	UP,
	LOAD,
	L,
	CE,
	ACLR);


output [15 : 0] Q;
input CLK;
input UP;
input LOAD;
input [15 : 0] L;
input CE;
input ACLR;

// synopsys translate_off

      C_COUNTER_BINARY_V6_0 #(
		"0000",	// c_ainit_val
		"0001",	// c_count_by
		2,	// c_count_mode
		"1111111111111111",	// c_count_to
		1,	// c_enable_rlocs
		1,	// c_has_aclr
		0,	// c_has_ainit
		0,	// c_has_aset
		1,	// c_has_ce
		0,	// c_has_iv
		1,	// c_has_l
		1,	// c_has_load
		0,	// c_has_q_thresh0
		0,	// c_has_q_thresh1
		0,	// c_has_sclr
		0,	// c_has_sinit
		0,	// c_has_sset
		0,	// c_has_thresh0
		0,	// c_has_thresh1
		1,	// c_has_up
		1,	// c_load_enable
		0,	// c_load_low
		0,	// c_pipe_stages
		0,	// c_restrict_count
		"0",	// c_sinit_val
		0,	// c_sync_enable
		1,	// c_sync_priority
		"1111111111111111",	// c_thresh0_value
		"1111111111111111",	// c_thresh1_value
		1,	// c_thresh_early
		16)	// c_width
	inst (
		.Q(Q),
		.CLK(CLK),
		.UP(UP),
		.LOAD(LOAD),
		.L(L),
		.CE(CE),
		.ACLR(ACLR),
		.IV(),
		.THRESH0(),
		.Q_THRESH0(),
		.THRESH1(),
		.Q_THRESH1(),
		.SCLR(),
		.SINIT(),
		.SSET(),
		.AINIT(),
		.ASET());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of counter is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of counter is "black_box"

endmodule