library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count_top is
    Port ( rst : in std_logic;
           clkin : in std_logic;
           ce : in std_logic;
           ld : in std_logic;
           up : in std_logic;
           din : in std_logic_vector(15 downto 0);
           dout : out std_logic_vector(15 downto 0);
		 multi_out: out std_logic_vector(15 downto 0);
		 hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic);
end count_top;

architecture Behavioral of count_top is
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component counter
	port (
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic;
	UP: IN std_logic;
	LOAD: IN std_logic;
	L: IN std_logic_VECTOR(15 downto 0);
	CE: IN std_logic;
	ACLR: IN std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of counter: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of counter: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.



-- You must compile the wrapper file counter.vhd when simulating
-- the core, counter. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".





component HEX2LED_4 
    Port ( HEX : in std_logic_vector(15 downto 0);
           LED1 : out std_logic_vector(6 downto 0);
           LED2 : out std_logic_vector(6 downto 0);
           LED3 : out std_logic_vector(6 downto 0);
           LED4 : out std_logic_vector(6 downto 0));
end component;

component vga_16 
    Port ( clk : in std_logic;
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic;
		 innum  : in std_logic_vector(15 downto 0);
		 innum0 : in std_logic_vector(15 downto 0); 
           innum1 : in std_logic_vector(6 downto 0);
           innum2 : in std_logic_vector(6 downto 0);
           innum3 : in std_logic_vector(6 downto 0);
		 innum4 : in std_logic_vector(6 downto 0));
end component;

signal clk,reset: std_logic;
signal N: std_logic_vector(23 downto 0);
signal do: std_logic_vector(15 downto 0);
signal HEX :  std_logic_vector(15 downto 0);
signal LED1 : std_logic_vector(6 downto 0);
signal LED2 : std_logic_vector(6 downto 0);
signal LED3 : std_logic_vector(6 downto 0);
signal LED4 : std_logic_vector(6 downto 0);

begin

process(clkin, N)
begin
if (clkin'event and clkin='1') then
	N<=N+1;
end if;
end process;

clk<=N(23);
reset<=not rst;

process(rst, clk,do)
begin
if rst='0' then
	multi_out<=(others=>'0');
elsif clk'event and clk='1' then
	multi_out<= do(15 downto 8) * do(7 downto 0);
end if;
end process;

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U1: counter
		port map (
			Q => do,
			CLK => CLK,
			UP => UP,
			LOAD => LD,
			L => Din,
			CE => CE,
			ACLR => RST);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
dout<=not do;

U2: HEX2LED_4 port map(do, led1,led2,led3,led4);

U3: vga_16 port map(clkin,hs,vs,r,g,b,do,do,led1,led2,led3,led4);

end Behavioral;