<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="counter" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
counter YourInstanceName (
    .Q(Q),
    .CLK(CLK),
    .UP(UP),
    .LOAD(LOAD),
    .L(L),
    .CE(CE),
    .ACLR(ACLR));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="counter" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component counter
    port (
    Q: OUT std_logic_VECTOR(15 downto 0);
    CLK: IN std_logic;
    UP: IN std_logic;
    LOAD: IN std_logic;
    L: IN std_logic_VECTOR(15 downto 0);
    CE: IN std_logic;
    ACLR: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : counter
        port map (
            Q =&gt; Q,
            CLK =&gt; CLK,
            UP =&gt; UP,
            LOAD =&gt; LOAD,
            L =&gt; L,
            CE =&gt; CE,
            ACLR =&gt; ACLR);
 
		</Template>
	</Folder>
</RootFolder>