?? counter.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in STD_LOGIC_VECTOR(15 downto 0); COUNT: inout STD_LOGIC_VECTOR(15 downto 0));
end counter;
architecture Behavioral of counter is
begin
process (CLK, RESET) begin if RESET='0' then COUNT <= (others=>'0'); elsif CLK='1' and CLK'event then if CE='1' then if LOAD='1' then COUNT <= DIN; else if DIR='1' then COUNT <= COUNT + 1; else COUNT <= COUNT - 1; end if; end if; end if; end if;end process;
end Behavioral;
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