# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = F:\Xilinx\OpenHard\HDL_file\test_ROMSET speedgrade = -6SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc2s15SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = cs144SET createndf = FalseSET designentry = VHDLSET devicefamily = Spartan2SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Single_Port_Block_Memory family Xilinx,_Inc. 5.0# END Select# BEGIN ParametersCSET handshaking_pins=falseCSET init_value=0CSET coefficient_file=F:\Xilinx\OpenHard\HDL_file\test_ROM\rom256x16.coeCSET select_primitive=4kx1CSET initialization_pin_polarity=Active_HighCSET global_init_value=0CSET depth=256CSET write_enable_polarity=Active_HighCSET port_configuration=Read_OnlyCSET enable_pin_polarity=Active_HighCSET component_name=rom256x16CSET active_clock_edge=Rising_Edge_TriggeredCSET additional_output_pipe_stages=0CSET limit_data_pitch=8CSET primitive_selection=Optimize_For_AreaCSET enable_pin=trueCSET init_pin=falseCSET write_mode=Read_After_WriteCSET has_limit_data_pitch=falseCSET load_init_file=trueCSET width=16CSET register_inputs=false# END ParametersGENERATE