<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="rom256x16" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
rom256x16 YourInstanceName (
    .addr(addr),
    .clk(clk),
    .dout(dout),
    .en(en));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="rom256x16" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component rom256x16
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    en: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : rom256x16
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout,
            en =&gt; en);
 
		</Template>
	</Folder>
</RootFolder>