library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity change is
port
( period,clk:in std_logic;
  n1,n2,n3:in std_logic_vector(3 downto 0);
  m1,m2,m3:in std_logic_vector(3 downto 0);
  P1,P2,P3:out std_logic_vector(3 downto 0)
);
end;

architecture a of change is
signal q1,q2,q3:std_logic_vector(3 downto 0);
begin
 process(clk)
 begin
if rising_edge(clk) then
if period='1' then
  q1<=n1;
  q2<=n2;
  q3<=n3;
 elsif period='0' then
  q1<=m1;
  q2<=m2;
  q3<=m3;  
  end if;
end if;
end process;
P1<=q1;
P2<=q2;
P3<=q3;
  end a;