?? signallatch.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SignalLatch is
port
(clock:in std_logic;
signal_in:in std_logic;
signal_out:out std_logic
);
end;
architecture a of SignalLatch is
signal m1,m2:std_logic;
begin
signal_out<=m2 and (not(m1));
process(clock)
begin
if rising_edge(clock) then
m1<=signal_in;
m2<=m1;
end if;
end process;
end a;
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