?? dds_sin.tan.rpt
字號:
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ; PLL output ; 250.0 MHz ; 0.000 ns ; 0.000 ns ; sysclk ; 5 ; 2 ; -1.833 ns ; ;
; sysclk ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; amp ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; bb ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; aa ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; cc ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'ppl2_5:ppl|altpll:altpll_component|_clk0' ;
+-----------------------------------------+-----------------------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[0] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[1] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[2] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[3] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[4] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[5] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[6] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[7] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[8] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.244 ns ; 235.63 MHz ( period = 4.244 ns ) ; QRD[3] ; QRD[9] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.983 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[0] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[1] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[2] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[3] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[4] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[5] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[6] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[7] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[8] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.184 ns ; 239.01 MHz ( period = 4.184 ns ) ; QRD[9] ; QRD[9] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.923 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[0] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[1] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[2] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[3] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[4] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
; -0.064 ns ; 246.06 MHz ( period = 4.064 ns ) ; QRD[0] ; QRD[5] ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; ppl2_5:ppl|altpll:altpll_component|_clk0 ; 4.000 ns ; 3.739 ns ; 3.803 ns ;
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