Library IEEE;
use IEEE.std_logic_1164.all;

entity BARRELL is
    port (
        IN0: in std_logic_vector (31 downto 0);
        S  : in std_logic_vector (4 downto 0);
        Y  : out std_logic_vector (31 downto 0)
         );
end BARRELL;

architecture RTL of BARRELL is
constant N : integer := 32;
constant M : integer := 5;
type arytype is array(M downto 0) of std_logic_vector(N-1 downto 0);
signal INTSIG, SIG01, SIG10: arytype;
signal ZEROS : std_logic_vector(N-1 downto 0);

begin

ZEROS <= (ZEROS'range => '0');
INTSIG(0) <= IN0;
muxgen : for j in 1 to M generate
         SIG10(j) <= INTSIG(j-1);
         SIG01(j) <= INTSIG(j-1)(N-2**(j-1)-1 downto 0) & ZEROS(2**(j-1)-1 downto 0);
         INTSIG(j) <= SIG10(j) when S(j-1) = '0' else SIG01(j);
end generate;

Y <= INTSIG(M);
end RTL;