?? full_adder.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity FULL_ADDER is
port (X,Y,Cin : In std_logic; Cout, Sum: Out std_logic);
end FULL_ADDER;
architecture behaviour of FULL_ADDER is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end;
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