Library IEEE;
use IEEE.std_logic_1164.all;

entity MANMUX is
    port (
        X: in std_logic_vector (31 downto 0);
        Y: in std_logic_vector (31 downto 0);
        BIGX:  in std_logic;
        TOOSMALL:   in std_logic;
        TOSHIFT: out std_logic_vector (24 downto 0);
        BIGMAN:  out std_logic_vector (24 downto 0)
         );
end MANMUX;

architecture RTL of MANMUX is
signal YMAN1, XMAN1 : std_logic_vector (24 downto 0);
signal X0, Y0 : std_logic;
constant F0 : std_logic_vector (31 downto 0) := "10000000" & "00000000" & "00000000" & "00000000";

begin

     X0 <= '0' when X = F0 else not X(23);
     Y0 <= '0' when Y = F0 else not Y(23);
     XMAN1 <= X(23) & X0 & X(22 downto 0);
     YMAN1 <= Y(23) & Y0 & Y(22 downto 0);

     TOSHIFT <= (TOSHIFT'range => '0') when TOOSMALL = '1' else YMAN1 when BIGX = '1' else XMAN1;
     BIGMAN <= XMAN1 when BIGX = '1' else YMAN1;

end RTL;