Library IEEE;
use IEEE.std_logic_1164.all;

entity EXT2_32to25 is
    port (
        LEFTOUT: in std_logic_vector (31 downto 0);
        MANSFT: out std_logic_vector (24 downto 0)
         );
end EXT2_32to25;

architecture RTL of EXT2_32to25 is

begin

MANSFT <= LEFTOUT (24 downto 0);

end RTL;