Library IEEE;
use IEEE.std_logic_1164.all;

entity BARRELR is
    port (
        IN0: in std_logic_vector (31 downto 0);
        SIGN : in std_logic;
        S  : in std_logic_vector (4 downto 0);
        Y  : out std_logic_vector (31 downto 0)
         );
end BARRELR;

architecture RTL of BARRELR is
constant N : integer := 32;
constant M : integer := 5;
type arytype is array(M downto 0) of std_logic_vector(N-1 downto 0);
signal INTSIG, SIG01, SIG10: arytype;
signal SIGNS : std_logic_vector(N-1 downto 0);

begin

sgen : for j in 0 to N-1 generate
       SIGNS(j) <= SIGN;
end generate;

INTSIG(0) <= IN0;

muxgen : for j in 1 to M generate
         SIG10(j) <= INTSIG(j-1);
         SIG01(j) <= SIGNS(2**(j-1)-1 downto 0) & INTSIG(j-1)(N-1 downto 2**(j-1));
         INTSIG(j) <= SIG10(j) when S(j-1) = '0' else SIG01(j);
end generate;

Y <= INTSIG(M);
end RTL;