?? manadd.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity MANADD is
port (BIGMAN, SMALLMAN : in std_logic_vector(24 downto 0);
MANSUM : out std_logic_vector (25 downto 0));
end MANADD;
architecture Structure of MANADD is
component Full_Adder
port (X, Y, Cin : in std_logic; Cout, Sum: out std_logic);
end component;
signal A, B, C: std_logic_vector (25 downto 0);
signal Cin: std_logic;
begin
A <= BIGMAN(24) & BIGMAN;
B <= SMALLMAN(24) & SMALLMAN;
Cin <= '0';
Stages : for i in 25 downto 0 generate
LowBit : if i=0 generate
FA: Full_Adder port map (A(0),B(0),Cin,C(0), MANSUM(0));
end generate;
OtherBits: if i/= 0 generate
FA: Full_Adder port map (A(i),B(i), C(i-1), C(i), MANSUM(i));
end generate;
end generate;
end;
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