+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                  ;
+----------------------------------+-----------------+-----------------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path     ;
+----------------------------------+-----------------+-----------------+----------------------------------+
; light.vhd                        ; yes             ; User VHDL File  ; D:/eda設計/VHDL/紅綠燈/light.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------+


+--------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary      ;
+-----------------------------------+--------------+
; Resource                          ; Usage        ;
+-----------------------------------+--------------+
; Total logic elements              ; 10           ;
; Total combinational functions     ; 7            ;
;     -- Total 4-input functions    ; 1            ;
;     -- Total 3-input functions    ; 1            ;
;     -- Total 2-input functions    ; 0            ;
;     -- Total 1-input functions    ; 5            ;
;     -- Total 0-input functions    ; 0            ;
; Combinational cells for routing   ; 0            ;
; Total registers                   ; 8            ;
; Total logic cells in carry chains ; 5            ;
; I/O pins                          ; 5            ;
; Maximum fan-out node              ; reduce_nor~0 ;
; Maximum fan-out                   ; 8            ;
; Total fan-out                     ; 46           ;
; Average fan-out                   ; 3.07         ;
+-----------------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |light                     ; 10 (10)     ; 8            ; 0           ; 5    ; 0            ; 2 (2)        ; 3 (3)             ; 5 (5)            ; 5 (5)           ; |light              ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------+
; State Machine - |light|current_state                                                  ;
+----------------------+----------------------+---------------------+-------------------+
; Name                 ; current_state.yellow ; current_state.green ; current_state.red ;
+----------------------+----------------------+---------------------+-------------------+
; current_state.red    ; 0                    ; 0                   ; 0                 ;
; current_state.green  ; 0                    ; 1                   ; 1                 ;
; current_state.yellow ; 1                    ; 0                   ; 1                 ;
+----------------------+----------------------+---------------------+-------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/eda設計/VHDL/紅綠燈/light.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Dec 08 22:08:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off light -c light
Info: Found 2 design units, including 1 entities, in source file light.vhd
    Info: Found design unit 1: light-one
    Info: Found entity 1: light
Info: Elaborating entity "light" for the top level hierarchy
Info: VHDL Case Statement information at light.vhd(37): OTHERS choice is never selected
Warning: VHDL Process Statement warning at light.vhd(39): signal "temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: State machine "|light|current_state" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|light|current_state"
Info: Encoding result for state machine "|light|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "current_state.yellow"
        Info: Encoded state bit "current_state.green"
        Info: Encoded state bit "current_state.red"
    Info: State "|light|current_state.red" uses code string "000"
    Info: State "|light|current_state.green" uses code string "011"
    Info: State "|light|current_state.yellow" uses code string "101"
Info: Implemented 15 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 3 output pins
    Info: Implemented 10 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Dec 08 22:08:44 2007
    Info: Elapsed time: 00:00:02