-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 04/25/2008 22:42:38      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk_gen"
BEGIN

    DEVICE = "EPM7032SLC44-5";

    "clk"                          : INPUT_PIN  = 43     ;
    "reset"                        : INPUT_PIN  = 4      ; -- LC1
    "ena_scan"                     : OUTPUT_PIN = 40     ; -- LC18
    "ena_1Hz"                      : OUTPUT_PIN = 33     ; -- LC24
    "flash_1Hz"                    : OUTPUT_PIN = 41     ; -- LC17
    "|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node1" : LOCATION   = LC20   ; -- PIN 38
    "|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node5" : LOCATION   = LC21   ; -- PIN 37
    "|LPM_ADD_SUB:247|addcore:adder|addcore:adder0|result_node6" : LOCATION   = LC22   ; -- PIN 36
    ":6"                           : LOCATION   = LC19   ; -- PIN 39  -- clk_scan_ff1
    ":7"                           : LOCATION   = LC23   ; -- PIN 34  -- clk_scan_ff0
    ":10"                          : LOCATION   = LC32   ; -- PIN 24  -- ena_two
    ":11"                          : LOCATION   = LC31   ; -- PIN 25  -- clk_2Hz_ff6
    ":12"                          : LOCATION   = LC30   ; -- PIN 26  -- clk_2Hz_ff5
    ":13"                          : LOCATION   = LC29   ; -- PIN 27  -- clk_2Hz_ff4
    ":14"                          : LOCATION   = LC28   ; -- PIN 28  -- clk_2Hz_ff3
    ":15"                          : LOCATION   = LC27   ; -- PIN 29  -- clk_2Hz_ff2
    ":16"                          : LOCATION   = LC26   ; -- PIN 31  -- clk_2Hz_ff1
    ":17"                          : LOCATION   = LC25   ; -- PIN 32  -- clk_2Hz_ff0

END;

INTERNAL_INFO "clk_gen"
BEGIN
	DEVICE = EPM7032SLC44-5;
	LC18    : LORAX = "G14R0,PA5R0C1";
	LC24    : LORAX = "G33R0";
	LC17    : LORAX = "G13R0,PA7R0C1";
	LC19    : LORAX = "G15R0,PA3R0C1";
	LC23    : LORAX = "G32R0,PA12R0C1";
	OH0R0P4 : LORAX = "G43R0,PA20R0C1";
	LC32    : LORAX = "G58R0,PA29R0C1";
	LC31    : LORAX = "G57R0,PA28R0C1";
	LC30    : LORAX = "G56R0,PA30R0C1";
	LC29    : LORAX = "G55R0,PA27R0C1";
	LC28    : LORAX = "G41R0,PA22R0C1";
	LC27    : LORAX = "G40R0,PA19R0C1";
	LC26    : LORAX = "G39R0,PA21R0C1";
	LC20    : LORAX = "G16R0,PA1R0C1";
	LC25    : LORAX = "G38R0,PA18R0C1";
	LC21    : LORAX = "G30R0,PA16R0C1";
	LC22    : LORAX = "G31R0,PA14R0C1";
END;