------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    14:21:52 11/17/2008 -- Design Name: -- Module Name:    d4to7 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D4to7 is
Port( Q : in std_logic_vector(3 downto 0);
Seg : out std_logic_vector(6 downto 0));
end D4to7;
architecture D4to7_Arch of D4to7 is
-- Segment encoding
-- a
-- ---
-- f | | b
-- --- <- g
-- e | | c
-- ---
-- d
begin
-- Conditional signal assignments
-- LED seg order=a,b,c,d,e,f,g
-- seg6,seg5,seg4,seg3,seg2,seg1,seg0
Seg <= "0000001" when q = "0000" else
		"1001111" when q = "0001" else
		"0010010" when q = "0010" else
		"0000110" when q = "0011" else
		"1001100" when q = "0100" else
		"0100100" when q = "0101" else
		"0100000" when q = "0110" else
		"0001111" when q = "0111" else
		"0000000" when q = "1000" else
		"0000100" when q = "1001" else
		"0001000" when q = "1010" else
		"1100000" when q = "1011" else
		"0110001" when q = "1100" else
		"1000010" when q = "1101" else
		"0110000" when q = "1110" else
		"0111000" when q = "1111" else
		"1111111";
end D4to7_Arch;