library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequency1Hz is
port( clk20Hz : in std_logic;
      clk1Hz : out std_logic);
end entity;
architecture behav of frequency1Hz is
signal tout : integer range 0 to 9;
signal clk: std_logic;
begin
  process(clk20Hz)
  begin
    if rising_edge(clk20Hz) then
      if tout=9 then   --計數10次，輸出翻轉一次
        tout<=0;
        clk<=not clk;
      else
        tout<=tout+1;
      end if;
    end if;
  end process;
clk1Hz<=clk;
end behav;