; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                               ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                  ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------+
; controller.vhd                   ; yes             ; User VHDL File  ; E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 44    ;
; Total combinational functions               ; 44    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 17    ;
;     -- 3 input functions                    ; 12    ;
;     -- <=2 input functions                  ; 15    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 39    ;
;     -- arithmetic mode                      ; 5     ;
; Total registers                             ; 23    ;
; I/O pins                                    ; 20    ;
; Maximum fan-out node                        ; hold  ;
; Maximum fan-out                             ; 23    ;
; Total fan-out                               ; 225   ;
; Average fan-out                             ; 2.59  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |controller                ; 44 (44)           ; 23 (23)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 20   ; 0            ; |controller         ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 23    ;
; Number of registers using Synchronous Clear  ; 1     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |controller|greenB~reg0    ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |controller|numA[0]~reg0   ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |controller|numB[0]~reg0   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------------------+
; Source assignments for Top-level Entity: |controller ;
+----------------+-------+------+----------------------+
; Assignment     ; Value ; From ; To                   ;
+----------------+-------+------+----------------------+
; POWER_UP_LEVEL ; Low   ; -    ; countnum[0]          ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[1]          ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[2]          ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[3]          ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[4]          ;
; POWER_UP_LEVEL ; Low   ; -    ; countnum[5]          ;
+----------------+-------+------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Oct 04 16:06:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off controller -c controller
Info: Found 2 design units, including 1 entities, in source file controller.vhd
    Info: Found design unit 1: controller-behav
    Info: Found entity 1: controller
Info: Elaborating entity "controller" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at controller.vhd(19): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 65 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 17 output pins
    Info: Implemented 45 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Oct 04 16:06:59 2008
    Info: Elapsed time: 00:00:03