package logic is
	type Bit_vector is array (Natural range <>) of Bit;
end logic;

use WORK.logic.all;

entity And2 is
	port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of And2 is
begin
	O1 <= I1 and I2;
end And2_archit;

entity Inverter is
	port( I1: Bit; O1: out Bit);
end Inverter;
architecture Inverter_archit of Inverter is
begin
	O1 <= Not I1;
end Inverter_archit;
	
entity Decoder is
	generic (N: Positive);
	port(Sel: Bit_vector(1 to N);
		 Dout: out Bit_vector(1 to 2 ** N ) );
end Decoder;

architecture Generic_structure of Decoder is
	signal Sel_bar: Bit;
	component And2
		port (I1,I2: Bit;O1: out Bit);
	end component;
	component Inverter
		port (I1: Bit;O1: out Bit);
	end component;
	component Decoder
		generic (M: Positive);
		port( Sel: Bit_vector(1 to M);
			  Dout: out Bit_vector( 1 to 2**M ) );
	end component;

	for all : Inverter use entity WORK.Inverter(Inverter_archit)
					port map(I1 => I1, O1 => O1);
	for all : And2 use entity WORK.And2(And2_archit)
				port map (I1,I2,O1);
	for all : Decoder use entity work.Decoder(Generic_structure)
				generic map(  N => M )
				port map (Sel => Sel,Dout => Dout);
begin 
	Invert_select:
	Inverter port map ( Sel(N),Sel_bar );
	Not_recursive:
	if N = 1 generate
		Dout(N) <= Sel (N);
		Dout(2**(N-1)+1) <= Sel_bar;
	end generate;
	Recursive:
	if N > 1 generate
		B1: block
			signal Temp: Bit_vector(1 to 2**(N-1) );
		begin
			N_minus_1: Decoder generic map(N-1)
							   port map(Sel(1 to N-1), Temp);
			For_each_output_from_N_minus_1:
			for I in 1 to 2**(N-1) generate
				And_each_N_minus_1_with_Sel:
					And2 port map (Temp(I),Sel(N),Dout(2*(I-1)+1));
				And_each_N_minus_1_with_Sel_bar:
					And2 port map (Temp(I),Sel_bar,Dout(2*I) );
			end generate;
		end block;
	end generate;
end  Generic_structure;