--------------------------------------------------------------------------------
--
--   AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source:  AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
--                       University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
--                  Verified     By whom?           Date         Simulator
--                  --------   ------------        --------     ------------
--  Syntax            yes   Champaka Ramachandran  Sept17, 92     ZYCAD
--  Functionality     yes   Champaka Ramachandran  Sept17, 92     ZYCAD
--------------------------------------------------------------------------------

--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;

entity E is
end;

architecture AA of E is
	component creg
	   port (
      RLD_BAR : in MVL7;
         load : in MVL7;
         decr : in MVL7;
          clk : in clock;
            D : in MVL7_VECTOR(11 downto 0);
	   RE : inout MVL7_VECTOR(11 downto 0);
    Rzero_bar : out MVL7
		 );
	end component;
									
signal RLD_BAR : MVL7;
signal load : MVL7;
signal decr : MVL7;
signal clk : clock;
signal D : MVL7_VECTOR(11 downto 0);
signal RE : MVL7_VECTOR(11 downto 0);
signal Rzero_bar : MVL7;

for all : creg use entity work.reg(reg);

begin

CREG1 : creg port map(
      RLD_BAR,
         load,
         decr,
          clk,
            D,
	   RE,
    Rzero_bar 
		     );

process

begin

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '1';

load <= '1';

decr <= '0';

D <= "0000";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '0')
report
"Assert 0 : < Rzero_bar /= 0 >"
severity warning;

assert (RE = "0000")
report
"Assert 1 : < RE /= 0000 >" 
severity warning;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '1';

load <= '1';

decr <= '0';

D <= "1111";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '1')
report
"Assert 2 : < Rzero_bar /= 1 >"
severity warning;

assert (RE = "1111")
report
"Assert 3 : < RE /= 1111 >" 
severity warning;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

load <= '0';

decr <= '0';

D <= "0000";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '0')
report
"Assert 4 : < Rzero_bar /= 0 >"
severity warning;

assert (RE = "0000")
report
"Assert 5 : < RE /= 0000 >" 
severity warning;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '1';

load <= '0';

decr <= '0';

D <= "1111";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '0')
report
"Assert 6 : < Rzero_bar /= 0 >"
severity warning;

assert (RE = "0000")
report
"Assert 7 : < RE /= 0000 >" 
severity warning;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

load <= '0';

decr <= '0';

D <= "1111";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '1')
report
"Assert 8 : < Rzero_bar /= 1 >"
severity warning;

assert (RE = "1111")
report
"Assert 9 : < RE /= 1111 >" 
severity warning;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '1';

load <= '0';

decr <= '0';

D <= "0000";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (Rzero_bar = '1')
report
"Assert 10 : < Rzero_bar /= 1 >"
severity warning;

assert (RE = "1111")
report
"Assert 11 : < RE /= 1111 >" 
severity warning;

wait for 1 ns;

--------------------
--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

D <= "1111";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

decr <= '1';

RLD_BAR <= '1';

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (RE = "1110")
report
"Assert 12 : < RE /= 1110 >" 
severity warning;

wait for 1 ns;

--------------------
--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

D <= "1110";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

decr <= '1';

RLD_BAR <= '1';

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (RE = "1101")
report
"Assert 13 : < RE /= 1101 >" 
severity warning;

wait for 1 ns;

--------------------
--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

D <= "1100";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

decr <= '1';

RLD_BAR <= '1';

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (RE = "1011")
report
"Assert 14 : < RE /= 1011 >" 
severity warning;

wait for 1 ns;

--------------------
--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

D <= "1000";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

wait for 1 ns;

--------------------

clk <= '0';

wait for 1 ns;

decr <= '1';

RLD_BAR <= '1';

wait for 4 ns;

clk <= '1';

wait for 4 ns;

assert (RE = "0111")
report
"Assert 15 : < RE /= 0111 >" 
severity warning;

wait for 1 ns;

--------------------
--------------------

clk <= '0';

wait for 1 ns;

RLD_BAR <= '0';

D <= "0000";

wait for 4 ns;

clk <= '1';

wait for 4 ns;

wait for 1 ns;

end process;
end AA;