?? 49_test.vhd
字號:
entity delta is
end entity;
architecture archi_delta of delta is
signal a : integer:=40;
signal b : integer:=30;
begin
process
begin
a <= b;
b <= a;
wait for 10 ns;
a <= 40;
b <= 30;
wait for 20 ns;
assert false
report "End of simulation"
severity error;
end process;
end;
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