library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;
 
entity tb_buffer is
end tb_buffer;

architecture test of tb_buffer is
component key_buffer 
port(key:in t_digital;
     clk:in std_logic;
     reset:in std_logic;
     new_time:out t_clock_time);
end component;

signal key: t_digital;
signal clk: std_logic:='0';
signal reset: std_logic;
signal new_time: t_clock_time;

for all:key_buffer use entity work.key_buffer(rtl);

begin
u1: key_buffer port map(key,clk,reset,new_time);

process
    begin
     key <= 3 after 10 ns,
            2 after 110 ns,
            1 after 210 ns,
            4 after 310 ns,
            4 after 410 ns,   
            0 after 510 ns,
            9 after 610 ns,
            7 after 710 ns;
     reset <= '0',
              '1' after 30 ns,
              '0' after 130 ns;
     wait for 1000 ns;
     assert false report "End of Simulation!"
     severity error;
     end process;
     
clk <= not clk after 50 ns;
end test;