LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bit_rtl_adder is
   port ( 
	  in1  : bit_vector;
	  in2  : bit_vector;
	  cntl : bit;
	  pout : out bit_vector
   );
end bit_rtl_adder; 
 
architecture func of bit_rtl_adder is
begin
p1: process(cntl)
   begin
	  if cntl='1' then
		 pout <= in1+in2;
      end if;
   end process;
end  func;