--
-- Module: 	DECODE_1
-- Design: 	CAM_Top
-- VHDL code:	 RTL / Combinatorial
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Decode 1 bit address into 2 binary bits
--		Generate an ENABLE bus
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 23, 1999
-- Version: 1.0
--
-- History: 
-- 	1.  09/21/99: Fixed comments
--
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
--library UNISIM;
--use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity DECODE_1 is
    port (
        ADDR		: in std_logic_vector (0 downto 0); -- declare as a vector
        ENABLE		: in std_logic;
        BINARY_ADDR	: out std_logic_vector (1 downto 0)
    );
end DECODE_1;

architecture DECODE_1_arch of DECODE_1 is
--
-- Components Declarations:
--
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';
--
-- Create the write enable signal for each CAM_RAMB4
DECODE: process (ADDR,ENABLE)
begin
	BINARY_ADDR <= ( others => '0');
	case ADDR(0) is
		when '0' => BINARY_ADDR(0) <= ENABLE;
		when '1' => BINARY_ADDR(1) <= ENABLE;
		when others => BINARY_ADDR <= ( others => 'X');
	end case;
end process DECODE;	
--									
end DECODE_1_arch;