This models are written in VHDL!Author is Ovidiu Lupas!MASTER modelgenerates PCI compliant signalschecks Target signal compliance with PCIchecks data received from Target for correctnessgenerates assertion reports if Target signals are not PCI compliantTARGET modelgenerates PCI compliant signalschecks Master signal compliance with PCIchecks data received from Master for correctnessgenerates assertion reports if Master signals are not PCI compliantDescriptionThe models are boardlevel simulation models and are useful in the testing phaseofthe PCI cores design. The models are 32 bit, 33 MHz PCI compliant but are easyupgradable to 64 bit, 66 MHz. The models are free; you can redistribute themand/or modify them under the terms of the GNU General Public License aspublished by the Free Software Foundation; either version 2 of the License, or(at your option) any later version.The models are distributed in the hope that they will be useful, but WITHOUT ANYWARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR APARTICULAR PURPOSE. See the GNU General Public License for more details.Current Status:design is available in VHDL from OpenCores CVS via <ahref="http://www.opencores.org/cvsweb.shtml/pci_core/vhdl_behav/">cvsweb</a>documentation will be available in short timeif needed, easy upgradable to 64 bit, 66 MHz