?? readme.txt
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*******************************************************************************
** Copyright (c) 2006 Xilinx, Inc.
** All Rights Reserved
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/ Version: 1.0
** \ \ Filename: readme.txt
** / / Timestamp: 20 July 2006
** /___/ /\
** \ \ / \
** \___\/\___\
**
**
** Device: Virtex-5
** Purpose:
** Readme file for contents of XAPP851.ZIP. These files are associated with
** the DDR1 memory controller softcore reference design outlined in XAPP851.
** 1. Implementation details:
** a. Synthesis/Simulation/Place & Route software used to develop
** reference design. Specific software settings also mentioned here
** if appropriate.
** b. Platform used for hardware verification testing
** 2. Source code file descriptions
** 3. Simulation code file descriptions
** 4. Build-related support file descriptions
** 5. General notes (if appropriate)
**
** Reference:
** XAPP851
** Revision History:
** Rev 1.0 - First created, RChiu/TMoriyama, 5/9/06
** Rev 1.1 - Final check, date updated for release, 5/11/06
** Rev 1.2 - Fixed bug with CL=2.5 read-write spacing. re-release. rchiu.
** 7/20/06
*******************************************************************************
*******************************************************************************
** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
** provided to you "as is". Xilinx and its licensors make and you
** receive no warranties or conditions, express, implied,
** statutory or otherwise, and Xilinx specifically disclaims any
** implied warranties of merchantability, non-infringement,or
** fitness for a particular purpose. Xilinx does not warrant that
** the functions contained in these designs will meet your
** requirements, or that the operation of these designs will be
** uninterrupted or error free, or that defects in the Designs
** will be corrected. Furthermore, Xilinx does not warrantor
** make any representations regarding use or the results of the
** use of the designs in terms of correctness, accuracy,
** reliability, or otherwise.
**
** LIMITATION OF LIABILITY. In no event will Xilinx or its
** licensors be liable for any loss of data, lost profits,cost
** or procurement of substitute goods or services, or for any
** special, incidental, consequential, or indirect damages
** arising from the use or operation of the designs or
** accompanying documentation, however caused and on any theory
** of liability. This limitation will apply even if Xilinx
** has been advised of the possibility of such damage. This
** limitation shall apply not-withstanding the failure of the
** essential purpose of any limited remedies herein.
**
** Copyright
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