-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: phy_data_write.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Write data path. One copy instantiated at phy_top for each DQS
--         strobe. This module itself instantiates output DDR flops for data,
--         mask, and DQS write strobe.
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Added RST90 support. 5/10/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library unisim ;
use unisim.vcomponents.all ;

library work;
use work.ddr1_parameters.all;

entity phy_data_write is
port(
	rst			: in	std_logic;
        rst90           : in    std_logic;
	clk0		: in	std_logic;
	clk90		: in	std_logic;

	-- internal interface
	wr_data		: in	std_logic_vector(dq_per_dqs*2 - 1 downto 0);
	wr_dm		: in	std_logic_vector(1 downto 0);
	wr_en		: in	std_logic;

	-- Memory interface
	DQ			: out	std_logic_vector(dq_per_dqs - 1 downto 0);
	DQ_T		: out	std_logic_vector(dq_per_dqs - 1 downto 0);
	DQS			: out	std_logic_vector(0 downto 0);
	DQS_T		: out	std_logic_vector(0 downto 0);
	DM			: out	std_logic_vector(0 downto 0);
	DM_T		: out	std_logic_vector(0 downto 0)
);

end phy_data_write;

-----------------------------------------------
architecture rtl of phy_data_write is

	signal clk180		: std_logic;
	signal clk270		: std_logic;

	signal wr_en_p		: std_logic;
	signal wr_en90		: std_logic;
	signal wr_en180		: std_logic;
	signal wr_en270		: std_logic;

	signal dqs_t270		: std_logic;

	--signal dqs_en		: std_logic;
	signal dq_en		: std_logic;

	signal wr_data90	: std_logic_vector(dq_per_dqs*2 - 1 downto 0);
	signal wr_data270	: std_logic_vector(dq_per_dqs*2 - 1 downto 0);


	signal wr_dm90		: std_logic_vector(1 downto 0);
	signal wr_dm270		: std_logic_vector(1 downto 0);

	signal LOGIC_0		: std_logic;
	signal LOGIC_1		: std_logic;

begin

	LOGIC_0	<= '0';
	LOGIC_1 <= '1';

	clk180 <= not clk0;
	clk270 <= not clk90;

	P_WR_EN_P : process( clk0 )
	begin
	if clk0'event and clk0='1' then
		if rst = '1' then
			wr_en_p <= '0';
		else
			wr_en_p <= wr_en;
		end if;
	end if;
	end process;

	P_0to270 : process( clk270 )
	begin
	if clk270'event and clk270='1' then
		if rst = '1' then
			dqs_t270 <= '0';
			wr_en270 <= '0';
			wr_data270 <= (others => '0');
			wr_dm270 <= (others => '0');
		else
			dqs_t270 <= not (wr_en or wr_en_p);
			wr_en270 <= wr_en;
			wr_data270 <= wr_data;
			wr_dm270 <= wr_dm;
		end if;
	end if;
	end process;

	P_270to180 : process( clk180 )
	begin
	if clk180'event and clk180='1' then
		if rst = '1' then
			wr_en180 <= '0';
		else
			wr_en180 <= wr_en270;
		end if;
	end if;
	end process;

	P_270to90 : process( clk90 )
	begin
	if clk90'event and clk90='1' then
		if rst90 = '1' then
			wr_en90 <= '0';
			wr_data90 <= (others => '0');
			wr_dm90 <= (others => '0');
		else
			wr_en90 <= wr_en270;
			wr_data90 <= wr_data270;
			wr_dm90 <= wr_dm270;
		end if;
	end if;
	end process;

	dq_en <= not wr_en90;

	-- should be placed in IOBFF
	ODDR_DQS_T : FDCPE
	port map (
	Q	=> DQS_T(0),
	C	=> clk180,
	CE	=> LOGIC_1,
	D	=> dqs_t270,
	CLR	=> LOGIC_0,
--	PRE	=> rst
	PRE	=> LOGIC_0
	);

	ODDR_DQS : ODDR
	generic map (
	DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
	INIT => '1',
	SRTYPE => "SYNC"
	)
	port map (
	Q	=> DQS(0),
	C	=> clk180,
	CE	=> LOGIC_1,
	D1	=> wr_en180,
	D2	=> LOGIC_0,
	R	=> LOGIC_0,
	S	=> LOGIC_0
	);

	G_DQ1 : for I in 0 to dq_per_dqs - 1 generate

	-- should be placed in IOBFF
	ODDR_DQ_T : FDCPE
	port map (
	Q	=> DQ_T(I),
	C	=> clk90,
	CE	=> LOGIC_1,
	D	=> dq_en,
	CLR	=> LOGIC_0,
	PRE	=> LOGIC_0
	);

	ODDR_DQ : ODDR
	generic map (
	DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
	INIT => '1',
	SRTYPE => "SYNC"
	)
	port map (
	Q	=> DQ(I),
	C	=> clk90,
	CE	=> LOGIC_1,
	D1	=> wr_data90(I),
	D2	=> wr_data90(I + dq_per_dqs),
	R	=> LOGIC_0,
	S	=> LOGIC_0
	);

	end generate;

	DM_T(0) <= '0';

	ODDR_DM : ODDR
	generic map (
	DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
	INIT => '1',
	SRTYPE => "SYNC"
	)
	port map (
	Q	=> DM(0),
	C	=> clk90,
	CE	=> LOGIC_1,
	D1	=> wr_dm90(0),
	D2	=> wr_dm90(1),
	R	=> LOGIC_0,
	S	=> LOGIC_0
	);

--	end generate;

end rtl;