-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: phy_ctrl_out.vhd
--  /   /        Date Last Modified: 5/11/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Non-address control output IOB flops
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Changed CK to vector. 5/11/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library unisim ;
use unisim.vcomponents.all ;

library work;
use work.ddr1_parameters.all;

entity phy_ctrl_out is
port(
	rst		: in	std_logic;
	clk0		: in	std_logic;

	-- internal interface
	cs_n_in		: in	std_logic_vector(no_of_cs - 1 downto 0);
	ras_n_in	: in	std_logic;
	cas_n_in	: in	std_logic;
	we_n_in		: in	std_logic;

	-- Memory interface
	CS_n		: out	std_logic_vector(no_of_cs - 1 downto 0);
	RAS_n		: out	std_logic;
	CAS_n		: out	std_logic;
	WE_n		: out	std_logic;
	CK		: out	std_logic_vector(clk_width - 1 downto 0)
);
end phy_ctrl_out;

-----------------------------------------------
architecture rtl of phy_ctrl_out is

	signal LOGIC_0		: std_logic;
	signal LOGIC_1		: std_logic;

	attribute iob: string;
	attribute iob of RAS_IOBFF	: label is "true";
	attribute iob of CAS_IOBFF	: label is "true";
	attribute iob of WE_IOBFF	: label is "true";

begin

	LOGIC_0	<= '0';
	LOGIC_1 <= '1';

	G_CS : for I in 0 to no_of_cs - 1 generate

		attribute iob of CS_IOBFF	: label is "true";

	begin

	CS_IOBFF : FDCPE
	port map (
	Q	=> CS_n(I),
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> cs_n_in(I),
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

	end generate;

	RAS_IOBFF : FDCPE
	port map (
	Q	=> RAS_n,
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> ras_n_in,
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

	CAS_IOBFF : FDCPE
	port map (
	Q	=> CAS_n,
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> cas_n_in,
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

	WE_IOBFF : FDCPE
	port map (
	Q	=> WE_n,
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> we_n_in,
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

        G_WR_DATA_FIFO: for I in 0 to clk_width-1 generate
        begin          
        ODDR_CK : ODDR
        generic map (
        DDR_CLK_EDGE => "OPPOSITE_EDGE",
        INIT => '1',
        SRTYPE => "SYNC"
        )
        port map (
        Q	=> CK(I),
        C	=> clk0,
        CE	=> LOGIC_1,
        D1	=> LOGIC_0,		-- rising edge
        D2	=> LOGIC_1,		-- falling edge
        R 	=> LOGIC_0,
        S	=> rst
        );
        end generate;

end rtl;