-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: phy_data_read.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Top-level for read capture logic. One copy instantiated at phy_top
--         for each DQS strobe. This module itself instantiates: (1) data read
--         calibration and capture logic (2) read enable calibration and
--         control logic.
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. 5/10/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library unisim ;
use unisim.vcomponents.all ;

library work;
use work.ddr1_parameters.all;

entity phy_data_read is
port(
	rst				: in	std_logic;
	clk0			: in	std_logic;

	-- internal interface
	rd_data			: out	std_logic_vector(dq_per_dqs*2 - 1 downto 0);
	rd_lat			: out	std_logic_vector(5 downto 0);
	latency			: in	std_logic_vector(3 downto 0);	-- Fixed latency
	rd_en_in		: in	std_logic;	-- from controller

	calib_start0	: in	std_logic;	-- calibration phase 1 starts
	calib_start1	: in	std_logic;	-- calibration phase 2 starts
	calib_done0		: out	std_logic;	-- calibration phase 1 done
	calib_done1		: out	std_logic;	-- calibration phase 2 done
	error			: out	std_logic;

	-- Memory interface
	DQ				: in	std_logic_vector(dq_per_dqs - 1 downto 0);
	DQS				: in	std_logic
);
end phy_data_read;

-----------------------------------------------
architecture rtl of phy_data_read is

	component phy_dq_align is
	port(
	rst			: in	std_logic;
	clk0		: in	std_logic;

	DQS			: in	std_logic;
	DQ			: in	std_logic_vector(dq_per_dqs - 1 downto 0);

	rd_data		: out	std_logic_vector(dq_per_dqs*2 - 1 downto 0);
	calib_start	: in	std_logic;
	calib_done	: out	std_logic
	);
	end component;

	component phy_rden_align is
	port(
	rst			: in	std_logic;
	clk0		: in	std_logic;

	rd_en_i		: in	std_logic;	-- From controller
	rd_data_i	: in	std_logic_vector(dq_per_dqs*2 - 1 downto 0);	-- From the read data capture logic

	rd_data_o	: out	std_logic_vector(dq_per_dqs*2 - 1 downto 0);	-- To UI
	rd_lat_o	: out	std_logic_vector(5 downto 0);	-- To UI

	latency		: in	std_logic_vector(3 downto 0);	-- Fixed latency
	calib_start	: in	std_logic;	-- From controller
	calib_done	: out	std_logic;	-- To controller. 	When 1, second calibration done
	error		: out	std_logic
	);
	end component;

	signal rd_data_aligned	: std_logic_vector(dq_per_dqs*2 - 1 downto 0);

begin

	PHY_DQ_ALIGN_I : phy_dq_align
	port map (
	rst			=> rst,
	clk0		=> clk0,

	DQS			=> DQS,
	DQ			=> DQ,

	rd_data		=> rd_data_aligned,
	calib_start	=> calib_start0,
	calib_done	=> calib_done0
	);

	PHY_RDEN_ALIGN_I : phy_rden_align
	port map(
	rst			=> rst,
	clk0		=> clk0,

	rd_en_i		=> rd_en_in,
	rd_data_i	=> rd_data_aligned,

	rd_data_o	=> rd_data,
	rd_lat_o	=> rd_lat,

	latency		=> latency,
	calib_start	=> calib_start1,
	calib_done	=> calib_done1,
	error		=> error
	);

end rtl;