-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: ddr1_parameters.vhd
--  /   /        Date Last Modified: 5/11/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: package file containing memory parameters and other constants
--         required by this design
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Added comments for
--              parameterization. Redid some of the parameterization to use
--              fixed dependencies on other paramters. Commented some unused
--              constants. 5/11/06.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

package ddr1_parameters is

-------------------------------------------------------------------------------
-- WIDTH PARAMETERS:
-- Guidelines for user (or MIG tool) for changing these parameters:
-- User configurable parameters:
--   # of DDR1 components used:      no_of_comps
--   # of chip select outputs (will vary w/ user board config): no_of_cs
--   # of DQ I/O per component:      dq_per_comp
--   # of DQ's per DQS (typ 8):      dq_per_dqs
--   # of DQ's per DM mask (typ 8):  dq_per_dm
--   # of bits in row address:       row_address
--   # of bits in column address:    column_address
--   # of bits in bank address:      bank_address
--   # of clock enable outputs:      cke_width
-- Dependent parameters (see below for formulae):
--   # of diff pair clock outputs (typ one per component): clk_width
--   # DQS signals per component:    dqs_per_comp
--   # Mask inputs per component:    dm_per_comp
--   total DDR1 bus data width:      data_width
--   total DDR1 DQS width:           data_strobe_width
--   total DM data mask width:       data_mask_width
--   # FIFO16's used for write FIFO: fifo_16
--     NOTE: Change if using V5 72-bit wide FIFOs in design
-------------------------------------------------------------------------------

-- User configurable parameters
constant   no_of_comps     : INTEGER :=  1;
constant   no_of_cs        : INTEGER :=  1;
constant   dq_per_comp     : INTEGER :=  16;
constant   dq_per_dqs      : INTEGER :=  8;		
constant   dq_per_dm       : INTEGER :=  8;     
constant   row_address     : INTEGER :=  13;
constant   column_address  : INTEGER :=  10;
constant   bank_address    : INTEGER :=  2;

-- Hardcoded, dependent parameters (change only if user using different
-- configuration than assumed - e.g. if clk_width = 1, but no_of_comps = 2)
constant   clk_width         : INTEGER :=  no_of_comps;	       
constant   dqs_per_comp      : INTEGER :=  dq_per_comp / dq_per_dqs;	      
constant   dm_per_comp       : INTEGER :=  dq_per_comp / dq_per_dm;
constant   data_width        : INTEGER :=  no_of_comps * dq_per_comp;
constant   data_strobe_width : INTEGER :=  no_of_comps * dqs_per_comp;
constant   data_mask_width   : INTEGER :=  no_of_comps * dm_per_comp;
constant   fifo_16           : INTEGER := (data_width * 2) / 32;

-- Unused parameters. May reserve for future expansion (or not..)
-- constant   cke_width       : INTEGER :=  1;
-- constant   RESET                                     : INTEGER   :=  0;
-- constant   tb_enable                                 : INTEGER   :=  1;
-- constant   dcm_enable                                : INTEGER   :=  1;
-- constant   dcm_disable                               : INTEGER   :=  0;

-------------------------------------------------------------------------------

constant    ecc_enable               : std_logic := '0';
constant    ecc_disable              : std_logic := '1';
constant    ecc_width                : integer := 0;
constant    registered               : std_logic := '0';
constant    unbuffered               : std_logic := '1';
constant    col_ap_width             : integer := 11;
constant    Phy_Mode                 : std_logic := '1';
constant    rcd_count_value          : std_logic_vector(2 downto 0) := "100";
constant    ras_count_value          : std_logic_vector(3 downto 0) := "1011";
constant    mrd_count_value          : std_logic := '1';
constant    rp_count_value           : std_logic_vector(2 downto 0) := "011";
constant    rfc_count_value          : std_logic_vector(5 downto 0) := "010011";
constant    trtp_count_value         : std_logic_vector(2 downto 0) := "011";
constant    twr_count_value          : std_logic_vector(2 downto 0) := "110";
constant    twtr_count_value         : std_logic_vector(2 downto 0) := "100";
constant    max_ref_width            : integer := 8;
constant    max_ref_cnt              : std_logic_vector(10 downto 0) := "00010000001";
constant    odt_enable		     : integer := 0;
constant    load_mode_register        : std_logic_vector(12 downto 0) := "0000000110010";
constant    load_mode_register_dllrst : std_logic_vector(12 downto 0) := "0000100110010";
constant    ext_load_mode_register    : std_logic_vector(12 downto 0) := "0000000000000";
constant    chip_address             : integer := 1;
constant    rc_count_value	     : std_logic_vector(3 downto 0) := "1111";   -- active to active same bank = tRC-1
constant    read_enables	     : integer := 1;
constant    burst_length	     : std_logic_vector(2 downto 0) := "010";
constant    burst_type               : std_logic := '0';
constant    cas_latency_value	     : std_logic_vector(2 downto 0) := "011";
constant    mode		     : std_logic := '0';
constant    dll			     : std_logic := '0';
constant    drive_strengh	     : std_logic := '0';


constant    cs_h0               : std_logic_vector(3 downto 0)  := "0000";
constant    cs_hE               : std_logic_vector(3 downto 0)  := "1110";
constant    cs_hD               : std_logic_vector(3 downto 0)  := "1101";
constant    cs_hB               : std_logic_vector(3 downto 0)  := "1011";
constant    cs_h7               : std_logic_vector(3 downto 0)  := "0111";
constant    cs_hF               : std_logic_vector(3 downto 0)  := "1111" ;
constant    add_const1          : std_logic_vector(15 downto 0) := X"0400" ;
constant    add_const2          : std_logic_vector(15 downto 0) := X"0100" ;
constant    add_const3          : std_logic_vector(15 downto 0) := X"0000" ;
constant    add_const4          : std_logic_vector(15 downto 0) := X"FBFF" ;

end ddr1_parameters;