-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: ddr1_backend_fifos.vhd
--  /   /        Date Last Modified: 5/11/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Instantiates FIFOs associated with User Interface (command/address
--         and write data FIFO)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Removed commented
--              ddr_wr_data_fifo_8 instantiation. Added generate statement
--              for write FIFO (to support wider data widths). 5/11/06.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.ddr1_parameters.all;

entity ddr1_backend_fifos is
	port( clk0		: in std_logic;
	      clk90		: in std_logic;
	      rst		: in std_logic;
	      app_af_addr	: in std_logic_vector(35 downto 0);
	      app_af_WrEn	: in std_logic;
	      ctrl_af_RdEn	: in std_logic;
	      af_addr		: out std_logic_vector(35 downto 0);
	      af_Empty		: out std_logic;
	      af_Almost_Full	: out std_logic;
	      app_Wdf_data	: in std_logic_vector((data_width*2 - 1) downto 0);
	      app_mask_data	: in std_logic_vector((data_mask_width*2 - 1) downto 0);
	      app_Wdf_WrEn	: in std_logic;
	      ctrl_Wdf_RdEn	: in std_logic;
	      Wdf_data		: out std_logic_vector((data_width*2 - 1) downto 0);
	      mask_data		: out std_logic_vector((data_mask_width*2 - 1) downto 0);
	      Wdf_Almost_Full	: out std_logic
	     );
end ddr1_backend_fifos;

architecture arch of ddr1_backend_fifos is

component ddr1_rd_wr_addr_fifo
	port( clk0		: in std_logic;
	      rst		: in std_logic;
	      app_af_addr	: in std_logic_vector(35 downto 0);
	      app_af_WrEn	: in std_logic;
	      ctrl_af_RdEn	: in std_logic;
	      af_addr		: out std_logic_vector(35 downto 0);
	      af_Empty		: out std_logic;
	      af_Almost_Full	: out std_logic
	    );
end component;

component ddr1_wr_data_fifo_16
	port( clk0		: in std_logic;
	      clk90		: in std_logic;
	      rst		: in std_logic;
	      app_Wdf_data	: in std_logic_vector(31 downto 0);
	      app_mask_data	: in std_logic_vector(3 downto 0);
	      app_Wdf_WrEn	: in std_logic;
	      ctrl_Wdf_RdEn	: in std_logic;
	      Wdf_data		: out std_logic_vector(31 downto 0);
	      mask_data		: out std_logic_vector(3 downto 0);
	      wr_df_almost_full : out std_logic
	     );
end component;

signal wr_df_almost_full_w : std_logic_vector(fifo_16-1 downto 0);

begin

Wdf_Almost_Full  <= wr_df_almost_full_w(0);

rd_wr_addr_fifo_00: ddr1_rd_wr_addr_fifo port map
	    ( clk0		=> clk0,
	      rst		=> rst,
	      app_af_addr	=> app_af_addr,
	      app_af_WrEn	=> app_af_WrEn,
	      ctrl_af_RdEn	=> ctrl_af_RdEn,
	      af_addr		=> af_addr,
	      af_Empty		=> af_Empty,
	      af_Almost_Full	=> af_Almost_Full
	    );

-- One FIFO for each 32-bits of User input (i.e. one FIFO for every
-- 16-bits of DDR data). NOTE: This should be rewritten more efficiently
-- for future rev to take advantage of V-5 built-in FIFO primitive being
-- able to handle 72-bits, and not 36-bits. Then again, MAP may be able
-- to use the "unused" half of a RAMB36 for an unrelated BRAM (still,
-- it's just cleaner to use the 72-bit FIFO here)
G_WR_DATA_FIFO: for I in 0 to fifo_16-1 generate
begin
wr_data_fifo_160 : ddr1_wr_data_fifo_16 port map
            ( clk0              => clk0,
              clk90             => clk90,
              rst               => rst,
              app_Wdf_data      => app_Wdf_data(32*(I+1)-1 downto 32*I),
              app_mask_data     => app_mask_data(4*(I+1)-1 downto 4*I),
              app_Wdf_WrEn      => app_Wdf_WrEn,
              ctrl_Wdf_RdEn     => ctrl_Wdf_RdEn,
              Wdf_data          => Wdf_data(32*(I+1)-1 downto 32*I),
              mask_data         => mask_data(4*(I+1)-1 downto 4*I),
              wr_df_almost_full => wr_df_almost_full_w(I)
            );
end generate;

end arch;