?? phy_top.vhd
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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.1
-- \ \ Filename: phy_top.vhd
-- / / Date Last Modified: 5/11/06
-- /___/ /\ Date Created:
-- \ \ / \
-- \___\/\___\
--
--Device: Virtex-5
--Purpose: Top-level for memory "physical-layer" PHY interface. User would
-- instantiate this module (instead of either hwtb_ddr1_top or
-- ddr1_top) if they want to use their own memory controller, and only
-- need to use the physical layer logic (i.e. read data calibration and
-- capture, SDRAM initialization). Contains: (1) All SDRAM-related
-- IOBs, (2) SDRAM initialization logic, (3) write data path, (4) read
-- data path - specifically read data calibration/capture. Also
-- instantiated directly in this file (in addition to the major PHY
-- sub-modules): (1) I/O buffers for data/mask/DQS, (2) shift register
-- delay-chain for internal read enable valid signal.
--Reference:
-- XAPP851
--Revision History:
-- Rev 0.1 - Created. Author: Toshihiko Moriyama. 1/04/06.
-- Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
-- Rev 1.1 - External release. Added header. Added RST90 support.
-- Renamed OBUFT_DQ instance to OBUFT_DM. Changed CK to
-- vector. 5/11/06.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library unisim ;
use unisim.vcomponents.all ;
library work;
use work.ddr1_parameters.all;
entity phy_top is
port(
rst : in std_logic;
rst90 : in std_logic;
clk0 : in std_logic;
clk90 : in std_logic;
-- IO signals (memory interface)
CKE : out std_logic;
CK : out std_logic_vector(clk_width - 1 downto 0);
AD : out std_logic_vector(row_address - 1 downto 0);
BA : out std_logic_vector(bank_address - 1 downto 0);
CS_n : out std_logic_vector(no_of_cs - 1 downto 0);
RAS_n : out std_logic;
CAS_n : out std_logic;
WE_n : out std_logic;
DM : out std_logic_vector(data_mask_width - 1 downto 0);
DQ : inout std_logic_vector(data_width - 1 downto 0);
DQS : inout std_logic_vector(data_strobe_width - 1 downto 0);
-- UI
phy_rdy : out std_logic;
phy_error : out std_logic;
phy_addr_in : in std_logic_vector(row_address - 1 downto 0);
phy_bank_in : in std_logic_vector(bank_address - 1 downto 0);
phy_cs_n_in : in std_logic_vector(no_of_cs - 1 downto 0);
phy_ras_n_in : in std_logic;
phy_cas_n_in : in std_logic;
phy_we_n_in : in std_logic;
phy_wr_data_in : in std_logic_vector(data_width*2 - 1 downto 0); -- Input write data with write command
phy_wr_en_in : in std_logic;
phy_wr_dm_in : in std_logic_vector(data_mask_width*2 - 1 downto 0);
phy_rd_data_o : out std_logic_vector(data_width*2 - 1 downto 0);
phy_rd_valid_o : out std_logic
);
end phy_top;
-----------------------------------------------
architecture rtl of phy_top is
component phy_adr_out is
port(
rst : in std_logic;
clk0 : in std_logic;
-- internal interface
addr_in : in std_logic_vector(row_address - 1 downto 0);
bank_in : in std_logic_vector(bank_address - 1 downto 0);
-- Memory interface
AD : out std_logic_vector(row_address - 1 downto 0);
BA : out std_logic_vector(bank_address - 1 downto 0)
);
end component;
component phy_ctrl_out is
port(
rst : in std_logic;
clk0 : in std_logic;
-- internal interface
cs_n_in : in std_logic_vector(no_of_cs - 1 downto 0);
ras_n_in : in std_logic;
cas_n_in : in std_logic;
we_n_in : in std_logic;
-- Memory interface
CS_n : out std_logic_vector(no_of_cs - 1 downto 0);
RAS_n : out std_logic;
CAS_n : out std_logic;
WE_n : out std_logic;
CK : out std_logic_vector(clk_width - 1 downto 0)
);
end component;
component phy_data_read is
port(
rst : in std_logic;
clk0 : in std_logic;
-- internal interface
rd_data : out std_logic_vector(dq_per_dqs*2 - 1 downto 0);
rd_lat : out std_logic_vector(5 downto 0);
latency : in std_logic_vector(3 downto 0); -- Fixed latency
rd_en_in : in std_logic; -- from controller
calib_start0 : in std_logic; -- calibration phase 1 starts
calib_start1 : in std_logic; -- calibration phase 2 starts
calib_done0 : out std_logic; -- calibration phase 1 done
calib_done1 : out std_logic; -- calibration phase 2 done
error : out std_logic;
-- Memory interface
DQ : in std_logic_vector(dq_per_dqs - 1 downto 0);
DQS : in std_logic
);
end component;
component phy_data_write is
port(
rst : in std_logic;
rst90 : in std_logic;
clk0 : in std_logic;
clk90 : in std_logic;
-- internal interface
wr_data : in std_logic_vector(dq_per_dqs*2 - 1 downto 0);
wr_dm : in std_logic_vector(1 downto 0);
wr_en : in std_logic;
-- Memory interface
DQ : out std_logic_vector(dq_per_dqs - 1 downto 0);
DQ_T : out std_logic_vector(dq_per_dqs - 1 downto 0);
DQS : out std_logic_vector(0 downto 0);
DQS_T : out std_logic_vector(0 downto 0);
DM : out std_logic_vector(0 downto 0);
DM_T : out std_logic_vector(0 downto 0)
);
end component;
component phy_init is
port(
rst : in std_logic;
clk0 : in std_logic;
-- from/to memory
-- During initialization, PHY controller issues commands
cke_o : out std_logic;
cs_n_o : out std_logic;
ras_n_o : out std_logic;
cas_n_o : out std_logic;
we_n_o : out std_logic;
addr_o : out std_logic_vector(row_address - 1 downto 0);
bank_o : out std_logic_vector(bank_address - 1 downto 0);
-- internal interface
init_done : out std_logic
);
end component;
component phy_ptn_gen is
port(
rst : in std_logic;
clk0 : in std_logic;
-- Handshaking signals with controller
init_done : in std_logic;
calib_start0 : out std_logic; -- calib_start
calib_start1 : out std_logic;
calib_done0 : in std_logic;
calib_done1 : in std_logic;
rd_rdy : out std_logic;
cs_n_o : out std_logic;
ras_n_o : out std_logic;
cas_n_o : out std_logic;
we_n_o : out std_logic;
addr_o : out std_logic_vector(row_address - 1 downto 0);
bank_o : out std_logic_vector(bank_address - 1 downto 0);
wr_data_o : out std_logic_vector(data_width*2 - 1 downto 0);
wr_en_o : out std_logic
);
end component;
-- States
TYPE DDR1_STATE_TYPE is (
WAIT_INIT_DONE_ST,
WAIT_CALIB_DONE_ST,
MAIN_ST
);
signal state_c : DDR1_STATE_TYPE;
signal state_n : DDR1_STATE_TYPE;
signal addr_i : std_logic_vector(row_address - 1 downto 0);
signal bank_i : std_logic_vector(bank_address - 1 downto 0);
signal cke_i : std_logic;
signal cs_n_i : std_logic_vector(no_of_cs - 1 downto 0);
signal ras_n_i : std_logic;
signal cas_n_i : std_logic;
signal we_n_i : std_logic;
signal rd_latency : std_logic_vector(3 downto 0);
signal rd_en_in_i : std_logic;
signal rd_en_brst : std_logic_vector(3 downto 0);
signal wr_data_i : std_logic_vector(data_width*2 - 1 downto 0);
signal wr_dm_i : std_logic_vector(data_mask_width*2 - 1 downto 0);
signal wr_en_i : std_logic;
signal calib_start0 : std_logic;
signal calib_start1 : std_logic;
signal calib_done0 : std_logic;
signal calib_done1 : std_logic;
signal calib_done0_i : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal calib_done1_i : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal error_i : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_rdy : std_logic;
type slv6Array is array (no_of_comps*dqs_per_comp - 1 downto 0) of std_logic_vector(5 downto 0);
signal rd_lat : slv6Array;
signal rd_lat8 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_lat7 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_lat6 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_lat5 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_lat4 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal rd_lat3 : std_logic_vector(no_of_comps*dqs_per_comp - 1 downto 0);
signal addr_init : std_logic_vector(row_address - 1 downto 0);
signal bank_init : std_logic_vector(bank_address - 1 downto 0);
signal cke_init : std_logic;
signal cs_n_init : std_logic;
signal ras_n_init : std_logic;
signal cas_n_init : std_logic;
signal we_n_init : std_logic;
signal init_done_i : std_logic;
signal addr_calib : std_logic_vector(row_address - 1 downto 0);
signal bank_calib : std_logic_vector(bank_address - 1 downto 0);
signal cs_n_calib : std_logic;
signal ras_n_calib : std_logic;
signal cas_n_calib : std_logic;
signal we_n_calib : std_logic;
signal wr_data_calib : std_logic_vector(data_width*2 - 1 downto 0);
signal wr_en_calib : std_logic;
signal phy_rd_data : std_logic_vector(data_width*2 - 1 downto 0);
signal phy_wr_data : std_logic_vector(data_width*2 - 1 downto 0);
signal phy_wr_dm : std_logic_vector(data_mask_width*2 - 1 downto 0);
signal DQ_in : std_logic_vector(dq_per_comp * no_of_comps - 1 downto 0);
signal DQ_o : std_logic_vector(dq_per_comp * no_of_comps - 1 downto 0);
signal DQ_T_o : std_logic_vector(dq_per_comp * no_of_comps - 1 downto 0);
signal DQS_in : std_logic_vector(dqs_per_comp * no_of_comps - 1 downto 0);
signal DQS_o : std_logic_vector(dqs_per_comp * no_of_comps - 1 downto 0);
signal DQS_T_o : std_logic_vector(dqs_per_comp * no_of_comps - 1 downto 0);
signal DM_o : std_logic_vector(dm_per_comp * no_of_comps - 1 downto 0);
signal DM_T_o : std_logic_vector(dm_per_comp * no_of_comps - 1 downto 0);
signal rd_en_A : std_logic_vector(3 downto 0);
signal rd_en_srl : std_logic;
signal phy_rdy_i : std_logic;
signal burst_length : std_logic_vector(2 downto 0);
signal command : std_logic_vector(3 downto 0); -- CS_n & RAS_n & CAS_n & WE_n
-- commands used in init phase
constant DESEL_CMD : std_logic_vector(3 downto 0) := "1111";
constant NOP_CMD : std_logic_vector(3 downto 0) := "0111";
constant BSTP_CMD : std_logic_vector(3 downto 0) := "0110";
constant PRECHARGE_CMD : std_logic_vector(3 downto 0) := "0010";
constant AUTOREF_CMD : std_logic_vector(3 downto 0) := "0001";
constant LMR_CMD : std_logic_vector(3 downto 0) := "0000";
constant ACT_CMD : std_logic_vector(3 downto 0) := "0011";
constant RD_CMD : std_logic_vector(3 downto 0) := "0101"; -- not auto precharge
constant WR_CMD : std_logic_vector(3 downto 0) := "0100"; -- not auto precharge
begin
burst_length <= load_mode_register(2 downto 0);
G_DQ : for I in 0 to no_of_comps * dq_per_comp - 1 generate
IOBUF_DQ : IOBUF
port map (
IO => DQ(I), O=> DQ_in(I), I => DQ_o(I), T => DQ_T_o(I)
);
end generate;
G_DQS : for I in 0 to no_of_comps * dqs_per_comp - 1 generate
IOBUF_DQS : IOBUF
port map (
IO => DQS(I), O => DQS_in(I), I => DQS_o(I), T => DQS_T_o(I)
);
end generate;
G_DM : for I in 0 to no_of_comps * dm_per_comp - 1 generate
OBUFT_DM : OBUFT
port map (
O => DM(I), I => DM_o(I), T => DM_T_o(I)
);
end generate;
CKE <= cke_i;
phy_rdy <= phy_rdy_i;
-------------------------------------------------------
-- DDR1 memory controller initialization state machine
-------------------------------------------------------
P_SM_NEXT : process(clk0)
begin
if clk0'event and clk0='1' then
if rst = '1' then
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