state_c <= WAIT_INIT_DONE_ST;
		else
			state_c <= state_n;
		end if;
	end if;
	end process;

	P_SM : process ( rst, state_c, init_done_i, rd_rdy )
	begin
	if rst='1' then
		state_n <= WAIT_INIT_DONE_ST;
	else
		case state_c is
		when WAIT_INIT_DONE_ST =>
			if init_done_i = '1' then
				state_n <= WAIT_CALIB_DONE_ST;
			else
				state_n <= WAIT_INIT_DONE_ST;
			end if;

		when WAIT_CALIB_DONE_ST =>
			if rd_rdy = '1' then
				state_n <= MAIN_ST;
			else
				state_n <= WAIT_CALIB_DONE_ST;
			end if;

		when MAIN_ST =>
			state_n <= MAIN_ST;

		when others =>
			state_n <= WAIT_INIT_DONE_ST;

		end case;
	end if;
	end process;

	P_OUT : process (clk0 )
	begin
	if clk0'event and clk0='1' then
		if rst='1' then
			cke_i		<= '0';
			cs_n_i		<= (others => '1');
			ras_n_i		<= '1';
			cas_n_i		<= '1';
			we_n_i		<= '1';
			addr_i		<= (others => '0');
			bank_i		<= (others => '0');
			wr_data_i	<= (others => '0');
			wr_dm_i		<= (others => '0');
			wr_en_i		<= '0';
			phy_rdy_i	<= '0';

		else
			case state_c is
			when WAIT_INIT_DONE_ST =>
				cke_i		<= cke_init;
				cs_n_i		<= (others => cs_n_init);
				ras_n_i		<= ras_n_init;
				cas_n_i		<= cas_n_init;
				we_n_i		<= we_n_init;
				addr_i		<= addr_init;
				bank_i		<= bank_init;
				wr_data_i	<= (others => '0');
				wr_dm_i		<= (others => '0');
				wr_en_i		<= '0';
				phy_rdy_i	<= '0';

			when WAIT_CALIB_DONE_ST =>
				cke_i		<= '1';
				cs_n_i		<= (others => cs_n_calib);
				ras_n_i		<= ras_n_calib;
				cas_n_i		<= cas_n_calib;
				we_n_i		<= we_n_calib;
				addr_i		<= addr_calib;
				bank_i		<= bank_calib;
				wr_data_i	<= wr_data_calib;
				wr_dm_i		<= (others => '0');
				wr_en_i		<= wr_en_calib;
				phy_rdy_i	<= '0';

			when MAIN_ST =>
				cke_i		<= '1';
				cs_n_i		<= phy_cs_n_in;
				ras_n_i		<= phy_ras_n_in;
				cas_n_i		<= phy_cas_n_in;
				we_n_i		<= phy_we_n_in;
				addr_i		<= phy_addr_in;
				bank_i		<= phy_bank_in;
				wr_data_i	<= phy_wr_data;
				wr_dm_i		<= phy_wr_dm;
				wr_en_i		<= phy_wr_en_in;
				phy_rdy_i	<= '1';

			when others =>
				cke_i		<= '0';
				cs_n_i		<= (others => '1');
				ras_n_i		<= '1';
				cas_n_i		<= '1';
				we_n_i		<= '1';
				addr_i		<= (others => '0');
				bank_i		<= (others => '0');
				wr_data_i	<= (others => '0');
				wr_dm_i		<= (others => '0');
				wr_en_i		<= '0';
				phy_rdy_i	<= '0';

			end case;
		end if;
	end if;
	end process;

	G_WR_ORDER : for I in 0 to no_of_comps * dqs_per_comp - 1 generate

		phy_wr_data(dq_per_dqs*2*(I+1)-1 downto dq_per_dqs*2*I) <=
							phy_wr_data_in(dq_per_dqs*(I+1)+dq_per_comp*no_of_comps-1 downto dq_per_dqs*I+dq_per_comp*no_of_comps) &
							phy_wr_data_in(dq_per_dqs*(I+1)-1 downto dq_per_dqs*I);

		phy_wr_dm(I*2+1 downto I*2) <= phy_wr_dm_in(I+dm_per_comp*no_of_comps) & phy_wr_dm_in(I);

	end generate;

	command <= AND_REDUCE(cs_n_i) & ras_n_i & cas_n_i & we_n_i;

	P_RD_EN : process(clk0)
	begin
	if clk0'event and clk0='1' then
		if rst='1' then
			rd_en_in_i <= '0';
			rd_en_brst <= (others => '0');
		else
			if command = RD_CMD then	-- if read
				case burst_length is
				when "001" =>
					rd_en_brst <= "1000";
				when "010" =>
					rd_en_brst <= "1100";
				when "011" =>
					rd_en_brst <= "1111";
				when others =>
					rd_en_brst <= rd_en_brst(2 downto 0) & '0';
				end case;
			elsif command = BSTP_CMD then	-- if read burst stop
				rd_en_brst <= (others => '0');
			else
				rd_en_brst <= rd_en_brst(2 downto 0) & '0';
			end if;
			rd_en_in_i <= rd_en_brst(3);
		end if;
	end if;
	end process;
	----------------------------------------------------------------

	PHY_ADR_OUT_I : phy_adr_out
	port map (
	rst			=> rst,
	clk0		=> clk0,

	-- internal interface
	addr_in		=> addr_i,
	bank_in		=> bank_i,

	-- Memory interface
	AD			=> AD,
	BA			=> BA
	);

	-- Control signals
	PHY_CTRL_OUT_I : phy_ctrl_out
	port map (
	rst			=> rst,
	clk0		=> clk0,

	-- internal interface
	cs_n_in		=> cs_n_i,
	ras_n_in	=> ras_n_i,
	cas_n_in	=> cas_n_i,
	we_n_in		=> we_n_i,

	-- Memory interface
	CS_n		=> CS_n,
	RAS_n		=> RAS_n,
	CAS_n		=> CAS_n,
	WE_n		=> WE_n,
	CK			=> CK
	);



	-- read data
	G_RD : for I in 0 to no_of_comps * dqs_per_comp - 1 generate

	PHY_DATA_READ_I : phy_data_read
	port map(
	rst				=> rst,
	clk0			=> clk0,

	-- internal interface
	rd_data			=> phy_rd_data(dq_per_dqs*2*(I+1) - 1 downto dq_per_dqs*2*I),
	rd_lat			=> rd_lat(I),
	latency			=> rd_latency,
	rd_en_in		=> rd_en_in_i,

	calib_start0	=> calib_start0,
	calib_start1	=> calib_start1,
	calib_done0		=> calib_done0_i(I),
	calib_done1		=> calib_done1_i(I),
	error			=> error_i(I),

	-- Memory interface
	DQ				=> DQ_in(dq_per_dqs*(I+1) - 1 downto dq_per_dqs*I),
	DQS				=> DQS_in(I)
	);

	rd_lat8(I) <= rd_lat(I)(5);
	rd_lat7(I) <= rd_lat(I)(4);
	rd_lat6(I) <= rd_lat(I)(3);
	rd_lat5(I) <= rd_lat(I)(2);
	rd_lat4(I) <= rd_lat(I)(1);
	rd_lat3(I) <= rd_lat(I)(0);

	-- rising edge group
	phy_rd_data_o(dq_per_dqs*(I+1)-1 downto dq_per_dqs*I)
							<= phy_rd_data(dq_per_dqs+dq_per_dqs*2*I-1 downto dq_per_dqs*2*I);
	-- falling edge group
	phy_rd_data_o(dq_per_dqs*(I+1)+dq_per_comp*no_of_comps-1 downto dq_per_dqs*I+dq_per_comp*no_of_comps)
							<= phy_rd_data(dq_per_dqs*2*(I+1)-1 downto dq_per_dqs+dq_per_dqs*2*I);


	end generate;

	-- pick max latency
	P_READ_LATENCY : process( clk0 )
	begin
	if clk0'event and clk0='1' then
		if rst='1' then
			rd_latency <= (others => '0');
		else
			if or_reduce(rd_lat8) = '1' then
				rd_latency <= "1000";
			elsif or_reduce(rd_lat7) = '1' then
				rd_latency <= "0111";
			elsif or_reduce(rd_lat6) = '1' then
				rd_latency <= "0110";
			elsif or_reduce(rd_lat5) = '1' then
				rd_latency <= "0101";
			elsif or_reduce(rd_lat4) = '1' then
				rd_latency <= "0100";
			elsif or_reduce(rd_lat3) = '1' then
				rd_latency <= "0011";
			else
				rd_latency <= "0000";
			end if;
		end if;
	end if;
	end process;

	rd_en_A <= unsigned(rd_latency) - CONV_UNSIGNED(1,4);
	phy_rd_valid_o <= rd_en_srl and phy_rdy_i;

	SRL16_RDEN : SRL16
	generic map (
	INIT => X"0000")
	port map (
	Q	=> rd_en_srl,
	A0	=> rd_en_A(0),
	A1	=> rd_en_A(1),
	A2	=> rd_en_A(2),
	A3	=> rd_en_A(3),
	CLK	=> clk0,
	D	=> rd_en_in_i
	);

	calib_done0 <= and_reduce(calib_done0_i);
	calib_done1 <= and_reduce(calib_done1_i);
	phy_error	<= or_reduce(error_i);

	-- Write IOB
	G_WR : for I in 0 to no_of_comps * dqs_per_comp - 1 generate

	PHY_DATA_WRITE_I : phy_data_write
	port map(
	rst			=> rst,
        rst90           => rst90,
	clk0		=> clk0,
	clk90		=> clk90,

	-- internal interface
	wr_data		=> wr_data_i(dq_per_dqs*2*(I+1) - 1 downto dq_per_dqs*2*I ),
	wr_dm		=> wr_dm_i(2*I+1 downto 2*I),
	wr_en		=> wr_en_i,

	-- Memory interface
	DQ			=> DQ_o(dq_per_dqs*(I+1) - 1 downto  dq_per_dqs*I),
	DQ_T		=> DQ_T_o(dq_per_dqs*(I+1) - 1 downto dq_per_dqs*I),
	DQS			=> DQS_o(I downto I),
	DQS_T		=> DQS_T_o(I downto I),
	DM			=> DM_o(I downto I),
	DM_T		=> DM_T_o(I downto I)
	);

	end generate;


	PHY_INIT_I : phy_init
	port map (
	rst				=> rst,
	clk0			=> clk0,

	-- To IOB
	cke_o			=> cke_init,
	cs_n_o			=> cs_n_init,
	ras_n_o			=> ras_n_init,
	cas_n_o			=> cas_n_init,
	we_n_o			=> we_n_init,
	addr_o			=> addr_init,
	bank_o			=> bank_init,

	init_done		=> init_done_i
	);


	PHY_PTN_GEN_I : phy_ptn_gen
	port map (
	rst				=> rst,
	clk0			=> clk0,

	-- Handshaking signals with controller
	init_done		=> init_done_i,
	calib_start0	=> calib_start0,
	calib_start1	=> calib_start1,
	calib_done0		=> calib_done0,
	calib_done1		=> calib_done1,
	rd_rdy			=> rd_rdy,

	cs_n_o			=> cs_n_calib,
	ras_n_o			=> ras_n_calib,
	cas_n_o			=> cas_n_calib,
	we_n_o			=> we_n_calib,
	addr_o			=> addr_calib,
	bank_o			=> bank_calib,
	wr_data_o		=> wr_data_calib,
	wr_en_o			=> wr_en_calib
	);

end rtl;