###############################################################################
## Copyright (c) 2006 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /   Vendor: Xilinx
## \   \   \/    Version: 1.0
##  \   \        Filename: hwtb_ddr1_top.prj
##  /   /        Date Last Modified: 5/10/06
## /___/   /\    Date Created:
## \   \  /  \
##  \___\/\___\
## 
##Device: Virtex-5
##Purpose: Sample Synplify Pro project file for DDR1 SDRAM Reference Design
##Reference:
##    XAPP851
##Revision History:
##    Rev 1.0 - External release. RChiu. 5/10/06.
###############################################################################

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.5 Virtex5 Beta
#-- Project file H:\projects\v5\ddr1\042906\syn\synplify\ddr1.prj
#-- Written on Fri May 05 16:54:54 2006


#add_file options
add_file -vhdl -lib work "../rtl/ddr1_parameters.vhd"
add_file -vhdl -lib work "../rtl/ddr1_wr_data_fifo_16.vhd"
add_file -vhdl -lib work "../rtl/ddr1_rd_wr_addr_fifo.vhd"
add_file -vhdl -lib work "../rtl/ddr1_backend_fifos.vhd"
add_file -vhdl -lib work "../rtl/ddr1_controller.vhd"
add_file -vhdl -lib work "../rtl/phy_ptn_Gen.vhd"
add_file -vhdl -lib work "../rtl/phy_init.vhd"
add_file -vhdl -lib work "../rtl/phy_ctrl_out.vhd"
add_file -vhdl -lib work "../rtl/phy_data_write.vhd"
add_file -vhdl -lib work "../rtl/phy_rden_align.vhd"
add_file -vhdl -lib work "../rtl/phy_dq_align.vhd"
add_file -vhdl -lib work "../rtl/phy_data_read.vhd"
add_file -vhdl -lib work "../rtl/phy_adr_out.vhd"
add_file -vhdl -lib work "../rtl/phy_top.vhd"
add_file -vhdl -lib work "../rtl/ddr1_top.vhd"
add_file -vhdl -lib work "../rtl/CLK_module.vhd"
add_file -vhdl -lib work "../rtl/PKG_PRBS.vhd"
add_file -vhdl -lib work "../rtl/hwtb_ddr1_top.vhd"
add_file -constraint "hwtb_ddr1_top.sdc"


#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology VIRTEX5
set_option -part XC5VLX50T
set_option -package FF1136
set_option -speed_grade -3

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "hwtb_ddr1_top"

#map options
set_option -frequency 1.000
set_option -run_prop_extract 0
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "rev_1/hwtb_ddr1_top.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -synthesis_onoff_pragma 0
set_option -dup 0
set_option -project_relative_includes 1
impl -active "rev_1"