###############################################################################
## Copyright (c) 2006 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /   Vendor: Xilinx
## \   \   \/    Version: 1.0
##  \   \        Filename: hwtb_ddr1_top.sdc
##  /   /        Date Last Modified: 5/10/06
## /___/   /\    Date Created:
## \   \  /  \
##  \___\/\___\
## 
##Device: Virtex-5
##Purpose: Sample Synplify Pro constraints for DDR1 SDRAM Reference Design
##Reference:
##    XAPP851
##Revision History:
##    Rev 1.0 - External release. RChiu. 5/10/06.
###############################################################################

# Synplicity, Inc. constraint file
# C:\projects\v5\ddr1\042906\syn\synplify\ddr1.sdc
# Written on Fri May 05 14:52:09 2006
# by Synplify Pro, Synplify Pro 8.5 Virtex5 Beta Scope Editor

#
# Collections
#

#
# Clocks
#
define_clock            -name {n:clk_in}  -freq 200.000 -clockgroup clk_in_clkgroup

#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_input_delay -disable      -default
define_output_delay -disable     -default
define_output_delay -disable     {AD[12:0]}
define_output_delay -disable     {BA[1:0]}
define_output_delay -disable     {CAS_n}
define_output_delay -disable     {CK_n[0]}
define_output_delay -disable     {CK_p[0]}
define_output_delay -disable     {CKE}
define_input_delay -disable      {clk_in_n}
define_input_delay -disable      {clk_in_p}
define_input_delay -disable      {clk200_in_n}
define_input_delay -disable      {clk200_in_p}
define_output_delay -disable     {CS_n[0]}
define_output_delay -disable     {ctrl_ready}
define_output_delay -disable     {dcm_locked}
define_output_delay -disable     {DM[1:0]}
define_input_delay -disable      {DQ[15:0]}
define_output_delay -disable     {DQ[15:0]}
define_input_delay -disable      {DQS[1:0]}
define_output_delay -disable     {DQS[1:0]}
define_output_delay -disable     {error}
define_output_delay -disable     {phy_error}
define_output_delay -disable     {RAS_n}
define_input_delay -disable      {rst_n}
define_output_delay -disable     {WE_n}

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#

#
# Path Delay
#

#
# Attributes
#
define_global_attribute          syn_useioff {1}

#
# I/O standards
#

#
# Compile Points
#

#
# Other Constraints
#