###############################################################################
## Copyright (c) 2006 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /   Vendor: Xilinx
## \   \   \/    Version: 1.0
##  \   \        Filename: do_hwtb_ddr1_top.prj
##  /   /        Date Last Modified: 5/10/06
## /___/   /\    Date Created:
## \   \  /  \
##  \___\/\___\
## 
##Device: Virtex-5
##Purpose: Sample Synplify Pro project file for DDR1 SDRAM Reference Design
##Reference:
##    XAPP851
##Revision History:
##    Rev 1.0 - Internal release. Toshihiko Moriyama. 4/29/06.
##    Rev 1.1 - External release. Added header, changed paths for source
##              files. 5/11/06.
###############################################################################

###############################################################################
# NOTES:
#  1. Assumes User has already created a work library and mapped "unisim" to 
#     existing compiled unisim VHDL library
#  2. Requires use of Mixed-Language simulator, since Micron DDR model is 
#     provided in Verilog only
###############################################################################

vcom -93 -work work ../rtl/ddr1_parameters.vhd
vcom -93 -work work ../rtl/pkg_PRBS.vhd
vcom -93 -work work ../rtl/phy_adr_out.vhd
vcom -93 -work work ../rtl/phy_ctrl_out.vhd
vcom -93 -work work ../rtl/phy_data_write.vhd
vcom -93 -work work ../rtl/phy_rden_align.vhd
vcom -93 -work work ../rtl/phy_dq_align.vhd
vcom -93 -work work ../rtl/phy_data_read.vhd
vcom -93 -work work ../rtl/phy_init.vhd
vcom -93 -work work ../rtl/phy_ptn_gen.vhd
vcom -93 -work work ../rtl/phy_top.vhd
vcom -93 -work work ../rtl/ddr1_backend_fifos.vhd
vcom -93 -work work ../rtl/ddr1_rd_wr_addr_fifo.vhd
vcom -93 -work work ../rtl/ddr1_wr_data_fifo_16.vhd
vcom -93 -work work ../rtl/ddr1_controller.vhd
vcom -93 -work work ../rtl/ddr1_top.vhd
vcom -93 -work work ../rtl/hwtb_ddr1_top.vhd
vcom -93 -work work ../rtl/CLK_module.vhd

# Memory simulation model
vlog -work work +incdir+. +define+sg5B +define+x16 +define+FULL_MEM ./ddr.v

# Testbench
vcom -93 -work work ./tb_hwtb_ddr1_top.vhd

# Load the design
vsim -t ps -L unisim work.tb_hwtb_ddr1_top

# wave
do wv_hwtb_ddr1_top.do

# Run simulation. Write/read test doesn't start until slightly after 204us
# when SDRAM initialization is complete. Can keep running this if you want, 
# read/write tests will continue forever
run 450 us