?? g_parity.vhd
字號(hào):
--*****************************************************************************
-- DESIGN : Parity Generator and Checker
-- FILE : G_PARITY.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESICNER: KA
-- Descr :
-- Entities: GEN_PAR
-- CHECK_PAR
-- ******************************************************
-- * Entities *
-- ******************************************************
--
-- Parity Generator
--
library IEEE;
use IEEE.std_logic_1164.all;
entity GEN_PAR is
port(
RESET : in std_logic;
CLK : in std_logic;
CE_ADo : in std_logic;
ADo : in std_logic_vector(31 downto 0);
CBEi : in std_logic_vector(3 downto 0);
NEW_PARo : out std_logic -- Generated Parity
);
end GEN_PAR;
--
-- Parity Checker
--
library IEEE;
use IEEE.std_logic_1164.all;
entity CHECK_PAR is
port(
RESET : in std_logic;
CLK : in std_logic;
ADi : in std_logic_vector(31 downto 0);
BEn : in std_logic_vector(3 downto 0);
FIRST_CYC : in std_logic; -- First Cycle After FRAME# falling edge
IRDYnid : in std_logic; --
TRDYnid : in std_logic; --
PARi : in std_logic; -- Chip Parity Input
PARid : in std_logic;
PERRni : in std_logic;
PERRnid : in std_logic;
SERRni : in std_logic;
SERRnid : in std_logic;
ACC_RD : in std_logic; --
ACC_WR : in std_logic; --
PERR_EN : in std_logic; -- Parity Error Response Enable
SERR_EN : in std_logic; -- SERR# Enable
TARGET_ACT : in std_logic; --
MASTER_READ : in std_logic; -- Command is Read
MASTER_ACT : in std_logic; -- Master Active
-- Outputs
NEW_PERRno : out std_logic; --
NEW_SERRno : out std_logic; --
NEW_OTPERR : out std_logic; -- Parity Error Buffer Control
SET_MDPERR : out std_logic; -- Set Master Data Parity Error Bit( 8)
SIG_SERR : out std_logic; -- Set Signaled System Error Bit (14)
DET_PERR : out std_logic -- Set Detected Parity Error Bit (15)
);
end CHECK_PAR;
-- ******************************************************
-- * Architectures *
-- ******************************************************
--
architecture RTL of GEN_PAR is
signal P: std_logic_vector (8 downto 0);
signal DataPar,CBEPar:std_logic;
begin
-- Parity Tree
PG0: P(0) <= ADo(0) xor ADo(1) xor ADo(2) xor ADo(3);
PG1: P(1) <= ADo(4) xor ADo(5) xor ADo(6) xor ADo(7);
PG2: P(2) <= ADo(8) xor ADo(9) xor ADo(10) xor ADo(11);
PG3: P(3) <= ADo(12) xor ADo(13) xor ADo(14) xor ADo(15);
PG4: P(4) <= ADo(16) xor ADo(17) xor ADo(18) xor ADo(19);
PG5: P(5) <= ADo(20) xor ADo(21) xor ADo(22) xor ADo(23);
PG6: P(6) <= ADo(24) xor ADo(25) xor ADo(26) xor ADo(27);
PG7: P(7) <= ADo(28) xor ADo(29) xor ADo(30) xor ADo(31);
PG8: P(8) <= P(0) xor P(1) xor P(2)xor P(3)xor P(4)xor P(5)xor P(6)xor
P(7);
pPDreg: process(CLK,RESET)
begin
if RESET='1' then --asynchronous RESET active High
DataPar <='0';
elsif (CLK'event and CLK='1') then --CLK rising edge
if CE_ADo='1' then
DataPar <= P(8);
end if;
end if;
end process;
PG9: CBEPar <= (CBEi(0) xor CBEi(1) xor CBEi(2) xor CBEi(3));
PG10:NEW_PARo <= CBEPar xor DataPar;
end RTL;-- of GEN_PAR ;
--
--
--
architecture RTL of CHECK_PAR is
signal P: std_logic_vector (8 downto 0);
signal Par,DPar,D_OTPERR,D_PERRDET,LOT_PERR,LDET_PERR: std_logic;
signal CmdErrPhase,CmdErr : std_logic;
signal ParDiff,DParDiff: std_logic;
signal LNEW_SERRno: std_logic;
signal MasterReadErr,MasterWriteErr: std_logic;
signal TargetWriteErr : std_logic;
signal TDValid: std_logic; -- Target Data Valid
signal MDValid: std_logic; -- Master Data Valid
-- signal MA1,CheckMaster:std_logic;
begin
pDValid: process(CLK,RESET)
begin
if RESET='1' then --asynchronous RESET active High
TDValid <='0';
MDValid <='0';
-- MA1 <= '0';
-- CheckMaster <= '0';
elsif (CLK'event and CLK='1') then --CLK rising edge
TDValid <= not(TRDYnid);
MDValid <= not(IRDYnid);
-- MA1 <= MASTER_ACT;
-- CheckMaster <= MA1;
end if;
end process;
-- Parity Tree
PG0: P(0) <= ADi(0) xor ADi(1) xor ADi(2) xor ADi(3);
PG1: P(1) <= ADi(4) xor ADi(5) xor ADi(6) xor ADi(7);
PG2: P(2) <= ADi(8) xor ADi(9) xor ADi(10) xor ADi(11);
PG3: P(3) <= ADi(12) xor ADi(13) xor ADi(14) xor ADi(15);
PG4: P(4) <= ADi(16) xor ADi(17) xor ADi(18) xor ADi(19);
PG5: P(5) <= ADi(20) xor ADi(21) xor ADi(22) xor ADi(23);
PG6: P(6) <= ADi(24) xor ADi(25) xor ADi(26) xor ADi(27);
PG7: P(7) <= ADi(28) xor ADi(29) xor ADi(30) xor ADi(31);
PG8: P(8) <= BEn(0) xor BEn(1) xor BEn(2) xor BEn(3);
PG9: Par <= P(0) xor P(1) xor P(2)xor P(3)xor P(4)xor P(5)xor P(6)xor
P(7)xor P(8);
--
ParDiff <= (Par xor PARi);
--
pDParDiff: process(CLK,RESET)
begin
if RESET='1' then --asynchronous RESET active High
DParDiff <='0';
elsif (CLK'event and CLK='1') then --CLK rising edge
DParDiff <= ParDiff;
end if;
end process;
-- Command Error detector (with FF)
pCmdErr: process(CLK,RESET)
begin
if RESET='1' then --asynchronous RESET active High
CmdErr <='0';
elsif (CLK'event and CLK='1') then --CLK rising edge
CmdErr <= ParDiff and FIRST_CYC;
end if;
end process;
-- SERR# generator
LNEW_SERRno <= not (ParDiff and SERR_EN and FIRST_CYC);
NEW_SERRno <= LNEW_SERRno;
-- Set Signaled System Error Bit (14)
pSigSERR: process(CLK,RESET)
begin
if RESET='1' then --asynchronous RESET active High
SIG_SERR <='0';
elsif (CLK'event and CLK='1') then --CLK rising edge
SIG_SERR <= not(LNEW_SERRno);
end if;
end process;
-- PERR# Generator
NEW_PERRno <= not((Par xor PARi)and PERR_EN);
-- LOT_PERR <= not((not(IRDYnid) and TARGET_ACT and ACC_WR) or
(not(TRDYnid) and CheckMaster and MASTER_READ));
LOT_PERR <= not((not(IRDYnid) and TARGET_ACT and ACC_WR));
NEW_OTPERR <= LOT_PERR;
LDET_PERR <=(DPar xor PARi);
-- Bad Parity detected during Target write transaction
TargetWriteErr <= DParDiff and MDValid and Target_ACT and ACC_WR;
-- Bad Parity detected during Master read transaction
-- MasterReadErr <= DParDiff and TDValid and CheckMaster and MASTER_READ;
-- Bad Parity signaled by Target during Master write transaction
-- MasterWriteErr <= CheckMaster and not(MASTER_READ) and not(PERRni);
-- Set Master Data Parity Error Bit( 8)
-- SET_MDPERR <= (MasterWriteErr or MasterReadErr)and PERR_EN;
SET_MDPERR <= '0';
-- Set Detected Parity Error Bit (15)
-- DET_PERR <= CmdErr or TargetWriteErr or MasterReadErr;
DET_PERR <= CmdErr or TargetWriteErr or MasterReadErr;
-- DFF 1 clock delay line
PP1: process(RESET,CLK)
begin
if RESET='1' then --asynchronous RESET active High
DPar <= '0';
D_OTPERR <= '1';
D_PERRDET <= '0';
elsif (CLK'event and CLK='1') then --CLK rising edge
DPar <= Par;
D_OTPERR <= LOT_PERR;
D_PERRDET<= LDET_PERR;
end if;
end process;
--
end RTL;
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