--*****************************************************************************
-- FILE    : PCI_IO_Virtex
-- DATE    : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr   : Physical I/O Interface to PCI Pins for VIRTEX family
-- Entities: PCI_IO_Virtex
--           PCILOGIC
-- Changes :
-- ******************************************************
-- *    Physical I/O Interface Entity                   *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity PCI_IO_Virtex is
  port (
      -- ## PCI Interface External Signals ## --
      RSTn_p     : in    std_logic;                     -- Reset
      CLK_p      : in    std_logic;                     -- Clock
       -- Address & Data
      AD_p       : inout std_logic_vector(31 downto 0); -- Address/Data Bus
      CBE_p      : in std_logic_vector(3 downto 0);  -- Command/Byte Enable
      PAR_p      : inout std_logic;                     -- Parity
      -- Interface Control
      FRAMEn_p   : in std_logic;                     -- Transaction Frame
      IRDYn_p    : in std_logic;                     -- Initiator Ready
      TRDYn_p    : inout std_logic;                     -- Target Ready
      DEVSELn_p  : inout std_logic;                     -- Device Select
      STOPn_p    : inout std_logic;                     -- Stop transaction
      IDSEL_p    : in    std_logic;                     -- Chip Select
      -- Error Reporting
      PERRn_p    : inout   std_logic;                   -- Parity Error 
(s/t/s)
      SERRn_p    : inout   std_logic;                   -- System Error 
(o/d)
      -- Interrupt
      INTAn_p    : out   std_logic;                     -- Interrupt pin 
(o/d)
      --### SYSTEM I/F Signals
      RESET      : out std_logic;                        -- Chip Reset
      CLK        : out std_logic;                        -- Chip Clock
      -- Address & Data
      ADi        : out std_logic_vector(31 downto 0);    -- Address/Data Bus 
  IN
      ADo        : in  std_logic_vector(31 downto 0);    -- Address/Data Bus 
  OUT
      CBEi       : out std_logic_vector(3 downto 0);     -- Command/Byte 
Enable Direct IN
      CBEid      : out std_logic_vector(3 downto 0);     -- Command/Byte 
Enable Registered IN
      PARi       : out std_logic;              -- Parity In  (-> Board)
      PARid      : out std_logic;              -- Parity In  (-> Board)
      PARo       : in  std_logic;                        -- Parity Out 
(Board ->)
      --### System Control signals
      -- Direct PCI Inputs
      IDSELi      : out std_logic;
      FRAMEni     : out std_logic;
      IRDYni      : out std_logic;
      DEVSELni    : out std_logic;
      TRDYni      : out std_logic;
      STOPni      : out std_logic;
      -- Registered PCI Inputs
      IDSELid     : out std_logic;
      FRAMEnid    : out std_logic;
      IRDYnid     : out std_logic;
      DEVSELnid   : out std_logic;
      TRDYnid     : out std_logic;
      STOPnid     : out std_logic;
      -- PCI Outputs
      NEW_DEVSELno: in  std_logic;
      NEW_TRDYno  : in  std_logic;
      NEW_STOPno  : in  std_logic;
      -- Tristate buffer control
      OT_DEVSEL   : in  std_logic;
      OT_TRDY     : in  std_logic;
      OT_STOP     : in  std_logic;
      T_OT_AD     : in  std_logic; 	-- Target DATA Output Tristate control
      CE_ADo      : in  std_logic;
      T_CE_ADoRDY : in  std_logic;

      -- Interrupt
      INTAno      : in   std_logic; -- Interrupt
      -- Error Reporting
      PERRni      : out   std_logic; -- Parity Error In
      SERRni      : out   std_logic; -- System Error In
      PERRnid     : out   std_logic; -- Parity Error In
      SERRnid     : out   std_logic; -- System Error In
      NEW_PERRno  : in   std_logic;  -- Parity Error Out
      NEW_OTPERR  : in   std_logic;  -- Parity Error Buffer Control
      NEW_SERRno  : in   std_logic  -- System Error Out
   );
  end PCI_IO_Virtex;
--
library ieee;
use ieee.std_logic_1164.all;
entity PCILOGIC is
    port (PCI_CE : out std_logic;
          IRDY   : in  std_logic;
          T_CE_RDY   : in  std_logic;
          DIR_CEo : in  std_logic
          );
end PCILOGIC;

--
--
architecture Struct of PCI_IO_Virtex is
  component FDCE is
      generic(
      TimingChecksOn: Boolean := FALSE);
      port(
      Q   :	out   std_logic;
      D   :	in    std_logic;
      C   :	in    std_logic;
      CE  :	in    std_logic;
      CLR :	in    std_logic);
  end component;
  component FDPE is
      generic(
      TimingChecksOn: Boolean := FALSE);
    port(
      Q   :	out   std_logic;
      D   :	in    std_logic;
      C   :	in    std_logic;
      CE  :	in    std_logic;
      PRE :	in    std_logic
    );end component;
  component IBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component BUFGP is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component OBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component OBUFT is
     port(
         I: in std_logic;
         O: out std_logic;
         T: in std_logic
     ); end component;
  component PCILOGIC
      port (
      PCI_CE: out std_logic;
      IRDY  : in  std_logic;
      T_CE_RDY: in  std_logic;
      DIR_CEo : in  std_logic
      );
   end component;
	-- Component declaration of the GEN_PAR unit
	-- File name contains GEN_PAR entity: .\G_PARITY.vhd
  component GEN_PAR
	port(
		RESET : in std_logic;
		CLK : in std_logic;
		CE_ADo : in std_logic;
		ADo : in std_logic_vector(31 downto 0);
		CBEi : in std_logic_vector(3 downto 0);
		NEW_PARo : out std_logic);
	end component;

   -- local signals
   signal CLKi, RESETn,RESETi : std_logic;
   signal IDSELil: std_logic;
   signal IRDYnil:  std_logic;
   signal TRDYnil:  std_logic;
   signal FRAMEnil:  std_logic;
   signal STOPnil: std_logic;
   signal LPARi: std_logic;
   signal DEVSELnil: std_logic;
   signal LGNTni  : std_logic;
   signal LPERRni  : std_logic;
   signal LSERRni  : std_logic;
--   signal FRAMEno:  std_logic;
--   signal IRDYno :  std_logic;
   signal DEVSELno : std_logic;
   signal TRDYno :  std_logic;
   signal STOPno : std_logic;
   signal L_OT_AD  : std_logic;
   signal OT_PAR,ParOut,PARod : std_logic;
   signal Log1,Log0 : std_logic;
   signal OT_ADo: std_logic_vector(31 downto 0);
   signal NEW_OT_ADo: std_logic;
   signal OT_CBE: std_logic_vector(3 downto 0);
   signal CE_ADob:std_logic_vector(3 downto 0);
   signal CBEc: std_logic_vector(3 downto 0);
   signal CBEod: std_logic_vector(3 downto 0);
   signal ADil: std_logic_vector(31 downto 0);
   signal ADol: std_logic_vector(31 downto 0);
   signal ADOT: std_logic_vector(31 downto 0);
   signal OT_IRDY: std_logic;
   signal PERRno: std_logic;
   signal SERRno: std_logic;
   signal OT_PERR : std_logic;
   signal OT_INTA : std_logic;
   signal T_OTAD, M_OTAD : std_logic;
   -- Component Attributes
   attribute IOB : string;
   attribute INIT : string;

begin
   Log0 <= '0';
   Log1 <= '1';
   -- #### RESET ####
   IB1: IBUF port map(I => RSTn_p, O => RESETn);
   AS1:RESETi <= not(RESETn);
   AS2:RESET  <= RESETi;
   -- #### Clock Buffer ####
   CB1: BUFGP port map(I => CLK_p, O => CLKi);-- Primary clock buffer
   AS3:CLK <= CLKi;
   -- #### TARGET SIGNALS ####
   -- IDSEL IOB
   IB2: IBUF port map(I => IDSEL_p, O => IDSELil);
   ASIO2:IDSELi <= IDSELil;                                                  
           -- Direct Input
   IFF2: FDCE port map(C=>CLKi, D=>IDSELil, Q=>IDSELid, CE=>Log1, 
CLR=>RESETi);	         -- Clocked Input
   -- FRAME# IOB
   IB3: IBUF port map(I => FRAMEn_p, O => FRAMEnil);                         
           -- Direct Input
   IFF3: FDPE  port map(C=> CLKi, D => FRAMEnil, Q => 
FRAMEnid,CE=>Log1,PRE=>RESETi);	   -- Clocked Input
   ASIO3:FRAMEni <= FRAMEnil;
   -- IRDY# IOB
   IB4: IBUF port map(I => IRDYn_p, O => IRDYnil); -- Direct Input
   IFF4: FDPE  port map(C=> CLKi, D => IRDYnil, Q => IRDYnid,CE=>Log1,PRE 
=>RESETi);	   -- Clocked Input
   ASIO4:IRDYni <= IRDYnil;
   -- TRDY# IOB
   IB5: IBUF port map(I => TRDYn_p, O => TRDYnil); -- Direct Input
   ASIO5:TRDYni <= TRDYnil;
   IFF5: FDPE  port map(C=> CLKi, D => TRDYnil, Q => 
TRDYnid,CE=>Log1,PRE=>RESETi);	   -- Clocked Input
   OFF5: FDPE  port map(C=> CLKi, D => NEW_TRDYno, Q => TRDYno,CE=>Log1,PRE 
=>RESETi);	   -- Clocked Input
   OB5: OBUFT port map(I=> TRDYno, O => TRDYn_p, T => OT_TRDY);
   -- STOP# IOB
   IB6: IBUF port map(I => STOPn_p, O => STOPnil);  -- Direct Input
   IFF6: FDPE  port map(C=> CLKi, D => STOPnil, Q => STOPnid, CE=>Log1, 
PRE=>RESETi);    -- Clocked Input
   OFF6: FDPE  port map(C=> CLKi, D => NEW_STOPno, Q => STOPno,CE=>Log1,PRE 
=>RESETi);	   -- Clocked Input
   OB6: OBUFT port map(I=> STOPno, O => STOPn_p, T => OT_STOP);
   ASIO6: STOPni <= STOPnil;
   -- DEVSEL# IOB
   IB7: IBUF port map(I => DEVSELn_p, O => DEVSELnil);    				-- Direct 
Input
   IFF7: FDPE  port map(C=> CLKi, D => DEVSELnil, Q => DEVSELnid, CE=>Log1, 
PRE=>RESETi);    -- Clocked Input
   OFF7: FDPE  port map(C=> CLKi, D => NEW_DEVSELno, Q => 
DEVSELno,CE=>Log1,PRE =>RESETi);	   -- Clocked Input
   OB7: OBUFT port map(I=> DEVSELno, O => DEVSELn_p, T => OT_DEVSEL);
   ASIO7: DEVSELni <= DEVSELnil;

   -- Interrupt Pin INTA# = Open Drain Output
   TFF8: FDPE  port map(C=> CLKi, D => INTAno, Q => OT_INTA,CE=>Log1,PRE 
=>RESETi);	   -- Clocked Input

   OB8: OBUFT port map(I=> Log0, O => INTAn_p  , T =>OT_INTA);
   --  C/BE#[3:0] Input
   CBEBUF:for I in 0 to 3 generate
      IBCBE: IBUF port map(I => CBE_p(I), O => CBEc(I));                     
              -- Input Buffer
      ASCBE: CBEi(I)<= CBEc(I);
      IFFCBE: FDCE  port map(C=> CLKi, D => CBEc(I), Q => CBEid(I), 
CE=>Log1, CLR=>RESETi); -- Clocked Input
   end generate;

   LPCI0 : PCILOGIC port map (
      PCI_CE => CE_ADob(0),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI1 : PCILOGIC port map (
      PCI_CE => CE_ADob(1),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI2 : PCILOGIC port map (
      PCI_CE => CE_ADob(2),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   LPCI3 : PCILOGIC port map (
      PCI_CE => CE_ADob(3),
      IRDY   => IRDYnil,
      T_CE_RDY   => T_CE_ADoRDY,
      DIR_CEo    => CE_ADo
      );
   -- DATA Output buffer control
   ASADT0: NEW_OT_ADo <= T_OT_AD;
   -- PCI Data Bus
   ADBUF0: for S in 0 to 7 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                          
              -- Input Buffer
      IFF : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, 
CLR=>RESETi);         -- Clocked Input
      OFF : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(0), 
CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => 
OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));         
                 -- Output Buffer
   end generate;
   ADBUF1: for S in 8 to 15 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                          
              -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, 
CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(1), 
CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => 
OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));         
                 -- Output Buffer
   end generate;
   ADBUF2: for S in 16 to 23 generate
      IBAD : IBUF port map(I=>AD_p(S), O=>ADil(S));                          
              -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, 
CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(2), 
CLR=>RESETi);       -- Clocked Output
      TFF : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => 
OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));         
                 -- Output Buffer
   end generate;
   ADBUF3: for S in 24 to 31 generate
      IBAD  : IBUF port map(I=>AD_p(S), O=>ADil(S));                         
               -- Input Buffer
      IFFAD : FDCE port map(C=>CLKi, D=>ADil(S), Q=>ADi(S), CE=>Log1, 
CLR=>RESETi);         -- Clocked Input
      OFFAD : FDCE port map(C=>CLKi, D=>ADo(S), Q=>ADol(S), CE=>CE_ADob(3), 
CLR=>RESETi);       -- Clocked Output
      TFF   : FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => 
OT_ADo(S),CE=>Log1,PRE =>RESETi);	   -- Clocked Input
      OBAD  : OBUFT port map(I=>ADol(S), O=> AD_p(S),  T=>OT_ADo(S));        
                  -- Output Buffer
   end generate;

   -- PARITY
	PG: GEN_PAR	port map(
   		RESET    => RESETi,
   		CLK      => CLKi,
   		CE_ADo   => CE_ADob(2),
   		ADo      => ADo,
   		CBEi     => CBEc,
   		NEW_PARo => ParOut
         );

   IBPAR : IBUF port map(I=> PAR_p, O=> LPARi);
   ASPAR : PARi <= LPARi;
   IFFPAR: FDCE port map(C => CLKi, D => LPARi, Q => PARid, CE => Log1, CLR 
=> RESETi);
   OTADFF: FDPE  port map(C=> CLKi, D => NEW_OT_ADo, Q => 
L_OT_AD,CE=>Log1,PRE =>RESETi);
   TFFPAR: FDPE port map(C => CLKi, D => L_OT_AD, Q => OT_PAR, CE => Log1, 
PRE =>RESETi);
   OFFPAR: FDCE port map(Q => PARod, D => ParOut, C => CLKi, CE => Log1, CLR 
=> RESETi);
   OBPAR : OBUFT port map(I=> PARod, O=> PAR_p,  T=>OT_PAR);
   -- Parity Error Reporting
   OFFPERR : FDCE port map(C => CLKi, D => NEW_PERRno, Q => PERRno, CE => 
Log1, CLR => RESETi);
   TFFERR: FDPE port map(C => CLKi, D => NEW_OTPERR, Q => OT_PERR, CE => 
Log1, PRE =>RESETi);
   PO2: OBUFT port map(I => PERRno, O => PERRn_p, T => OT_PERR);
--   PO2: OBUFT port map(I => Log0, O => PERRn_p, T => Log1);
   PI2: IBUF port map(I => PERRn_p, O => LPERRni);    				-- Direct Input
   PERRni <= LPERRni;
   IFFPERR : FDCE port map(C => CLKi, D =>LPERRni, Q =>PERRnid, CE => Log1, 
CLR => RESETi);

   -- System Error Reporting
   FFTSERR: FDPE port map(C => CLKi, D => NEW_SERRno, Q => SERRno, CE => 
Log1, PRE =>RESETi);
   PO3: OBUFT port map(I => Log0, O => SERRn_p, T => SERRno);
   PI3: IBUF port map(I => SERRn_p, O => LSERRni);    				-- Direct Input
   SERRni <= LSERRni;
   IFFSERR : FDCE port map(C => CLKi, D =>LSERRni, Q =>SERRnid, CE => Log1, 
CLR => RESETi);
   -- Bus Hanshake Signals
end Struct;
--
architecture RTL of PCILOGIC is
begin
   PCI_CE <= DIR_CEo or (T_CE_RDY and not IRDY);
end RTL;