?? cfg_regs.vhd
字號:
--*****************************************************************************
-- FILE : PCI_CFGREG
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Configuration Space Registers for Target-only Interface
-- Entities:
-- CFG_STREG
-- CFG_CMDREG
-- BAR_REG
-- EBAR
-- CFG_INTREG
-- Changes :
-- 4.8.1999 - CFG_STREG - added PCR_STAT port for register contens
-- visibility
-- - CFG_CMDREG - added PCR_CMD port for register contens
-- visibility
--
--*****************************************************************************
--* Command Register
*
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_CMDREG is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(15 downto 0);-- Data IN
DOUT : out std_logic_vector(15 downto 0);-- Data OUT
BEn : in std_logic_vector(3 downto 0); -- Byte Enables
WE : in std_logic;
OE : in std_logic;
PCR_CMD : out std_logic_vector(15 downto 0); -- PCI Cfg. Command
reg.
IO_EN : out std_logic; -- I/O Space Decoding Enabled
MEM_EN : out std_logic; -- Memory Space Decoding Enabled
SPEC_CYC : out std_logic; -- Special Cycles Monitoring Enabled
PERR_EN : out std_logic; -- Parity Error Response
STEPPING_EN : out std_logic; -- Stepping Control
SERR_EN : out std_logic -- SERR# Enable
);
end CFG_CMDREG;
--
-- Command Register RTL Architecture
--
architecture RTL of CFG_CMDREG is
signal Settings : std_logic_vector(15 downto 0);
begin
-- Register
INTREG: process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
Settings <= COMMAND_INIT;
elsif (CLK'event and CLK='1') then --CLK rising edge
if WE = '1' then
if BEn(0)='0' then
Settings(1 downto 0) <= DIN(1 downto 0);
Settings(2) <= '0'; -- Master not supported
Settings(3) <= DIN(3);
Settings(4) <= '0'; -- MWI not supported
Settings(5) <= '0';
Settings(6) <= DIN(6);
Settings(7) <= '0';
-- Settings(7) <= DIN(7); -- Stepping not supported
end if;
if BEn(1)='0' then
Settings(15 downto 10) <= "000000";
Settings(9 downto 8) <= DIN(9 downto 8);
end if;
end if;
end if;
end process;
-- Output Tristate Buffer
O_BUF: DOUT <= Settings when OE='1' else "ZZZZZZZZZZZZZZZZ";
PCR_CMD <= Settings; -- Command Register bits assignment
IO_EN <= Settings(0); -- I/O Space Decoding Enabled
MEM_EN <= Settings(1); -- Memory Space Decoding Enabled
SPEC_CYC <= Settings(3); -- Special Cycles Monitoring Enabled
PERR_EN <= Settings(6); -- Parity Error Response
STEPPING_EN <= Settings(7);-- Stepping Control
SERR_EN <= Settings(8);-- SERR# Enable
end RTL; -- CFG_CMDREG
--
--*****************************************************************************
--* Status Register
*
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_STREG is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(15 downto 0);-- Data IN
DOUT : out std_logic_vector(15 downto 0);-- Data OUT
BEn : in std_logic_vector(3 downto 0);
WE : in std_logic;
OE : in std_logic;
SET_MDPERR: in std_logic; -- Set Master Data Parity Error Bit( 8)
SIG_TABORT: in std_logic; -- Set Signaled Target Abort Bit (11)
RCV_TABORT: in std_logic; -- Set Received Target Abort Bit (12)
RCV_MABORT: in std_logic; -- Set Received Master Abort Bit (13)
SIG_SERR : in std_logic; -- Set Signaled System Error Bit (14)
DET_PERR : in std_logic; -- Set Detected Parity Error Bit (15)
PCR_STAT : out std_logic_vector(15 downto 0) -- PCI Cfg. Status
Register Contens
); end CFG_STREG;
--
-- Status Register RTL Architecture
--
architecture RTL of CFG_STREG is
signal Status : std_logic_vector(15 downto 0);
begin
Status(7 downto 0) <= STATUS_INIT(7 downto 0);
Status(10 downto 9) <= STATUS_INIT(10 downto 9);
--
CSRREG: process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
Status(15) <= STATUS_INIT(15);
Status(14) <= STATUS_INIT(14);
Status(13) <= STATUS_INIT(13);
Status(12) <= STATUS_INIT(12);
Status(11) <= STATUS_INIT(11);
Status(8) <= STATUS_INIT(8);
elsif (CLK'event and CLK='1') then --CLK rising edge
if (WE = '1') and (BEn(3)='0')then
-- RESET of Status Bits
if DIN(15)='1' then
Status(15) <='0';
end if;
if DIN(14)='1' then
Status(14) <='0';
end if;
if DIN(13)='1' then
Status(13) <='0';
end if;
if DIN(12)='1' then
Status(12) <='0';
end if;
if DIN(11)='1' then
Status(11) <='0';
end if;
if DIN(8)='1' then
Status(8) <='0';
end if;
else
if DET_PERR = '1' then
Status(15) <='1';
end if;
if SIG_SERR = '1' then
Status(14) <='1';
end if;
if RCV_MABORT = '1' then
Status(13) <='1';
end if;
if RCV_TABORT = '1' then
Status(12) <='1';
end if;
if SIG_TABORT = '1' then
Status(11) <='1';
end if;
if SET_MDPERR = '1' then
Status(8) <='1';
end if;
end if;
end if;
end process;
-- Output Tristate Buffer
O_BUF: DOUT <= Status when OE='1' else "ZZZZZZZZZZZZZZZZ";
PCR_STAT <= Status;
end RTL; -- CFG_STREG
--
--*****************************************************************************
--* Generic Base Address Register
*
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity BAR_REG is
generic(
BAR_NO: integer:= 0);
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(31 downto 0);-- Data In Bus
DOUT : out std_logic_vector(31 downto 0);-- Data Out Bus
BEn : in std_logic_vector(3 downto 0); -- Byte Enables
RD : in std_logic;
WR : in std_logic;
ACC_SPACE : in std_logic;
FIRST_CYC : in std_logic; -- First Cycle After FRAME# falling edge
HIT : out std_logic; -- BAR Hit = address is in BAR range
SIZE : out std_logic);-- BAR contains all 1's - cfg info will
be read
end BAR_REG;
--
-- BAR_REG RTL Architecture Description
--
architecture RTL of BAR_REG is
constant HI_Z_32 : std_logic_vector(31 downto 0):=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
signal Base_Adr : std_logic_vector(31 downto 0);
signal Base_Size : std_logic;
signal Base_Hit : std_logic;
signal SZ: std_logic_vector(8 downto 0);
begin
-- BASE ADDRESS Register
pADRREG: process(CLK,RESET)
begin
if (RESET = '1') then
Base_Adr <= (others=>'0');
elsif (CLK'event and CLK='1') then
if (WR = '1') then
if BEn(0)='0' then
Base_Adr(7 downto 0) <= DIN(7 downto 0);
end if;
if BEn(1)='0' then
Base_Adr(15 downto 8) <= DIN(15 downto 8);
end if;
if BEn(2)='0' then
Base_Adr(23 downto 16) <= DIN(23 downto 16);
end if;
if BEn(3)='0' then
Base_Adr(31 downto 24) <= DIN(31 downto 24);
end if;
end if;
end if;
end process pADRREG;
-- Address comparator
pADRCMP: process (FIRST_CYC,ACC_SPACE,DIN,Base_Adr)
begin
if (FIRST_CYC = '1') and (ACC_SPACE = '1') and
(DIN(31 downto (32-BAR_SET(BAR_NO).DWIDTH)) = Base_Adr(31 downto
(32-BAR_SET(BAR_NO).DWIDTH))) then
Base_Hit <= '1';
else
Base_Hit <= '0';
end if;
end process pADRCMP;
-- All 1's detector
D_S0: SZ(0)<= Base_Adr(31)and Base_Adr(30)and Base_Adr(29)and
Base_Adr(28);
D_S1: SZ(1)<= Base_Adr(27)and Base_Adr(26)and Base_Adr(25)and
Base_Adr(24);
D_S2: SZ(2)<= Base_Adr(23)and Base_Adr(22)and Base_Adr(21)and
Base_Adr(20);
D_S3: SZ(3)<= Base_Adr(19)and Base_Adr(18)and Base_Adr(17)and
Base_Adr(16);
D_S4: SZ(4)<= Base_Adr(15)and Base_Adr(14)and Base_Adr(13)and
Base_Adr(12);
D_S5: SZ(5)<= Base_Adr(11)and Base_Adr(10)and Base_Adr(9)and Base_Adr(8);
D_S6: SZ(6)<= Base_Adr(7)and Base_Adr(6)and Base_Adr(5)and Base_Adr(4);
D_S7: SZ(7)<= SZ(0)and SZ(1) and SZ(2) and SZ(3);
D_S8: Base_Size <= SZ(4)and SZ(7) and SZ(5) and SZ(6);
-- Data output tri-state buffer
D_BUF1: DOUT(31 downto 4)<= Base_Adr (31 downto 4) when RD = '1' else
HI_Z_32(31 downto 4);
D_BUF2: DOUT(3 downto 0) <= BAR_SET(BAR_NO).BARMAP(3 downto 0) when RD =
'1' else "ZZZZ";
-- Output Assignment
HIT <= Base_Hit when BAR_SET(BAR_NO).PRESENT else '0';
SIZE <= Base_Size when BAR_SET(BAR_NO).PRESENT else '1';
end RTL;
--
--*****************************************************************************
--* Expansion ROM Base Address Register
*
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity EBAR is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
BEn : in std_logic_vector(3 downto 0); -- Byte Enables
RD : in std_logic;
WR : in std_logic;
ACC_SPACE: in std_logic;
FIRST_CYC: in std_logic; -- First Cycle After FRAME# falling edge
HIT : out std_logic;
SIZE : out std_logic
);
end EBAR;
--
-- Expansion ROM BAR RTL Architecture Description
--
architecture RTL of EBAR is
constant HI_Z_32 : std_logic_vector(31 downto 0):=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant C_0x00000000 : std_logic_vector(31 downto 0):=
"00000000000000000000000000000000";
constant C_0xffffffff : std_logic_vector(31 downto 0):=
"11111111111111111111111111111111";
signal Base_Adr : std_logic_vector(31 downto 0);
signal Base_Size : std_logic;
signal Base_Hit : std_logic;
begin
-- BASE ADDRESS Register
ADRREG: process(CLK,RESET)
begin
if (RESET = '1') then
Base_Adr <= C_0x00000000 ;
elsif (CLK'event and CLK='1') then
if (WR = '1') then
if BEn(0)='0' then
Base_Adr(7 downto 0) <= DIN(7 downto 0);
end if;
if BEn(1)='0' then
Base_Adr(15 downto 8) <= DIN(15 downto 8);
end if;
if BEn(2)='0' then
Base_Adr(23 downto 16) <= DIN(23 downto 16);
end if;
if BEn(3)='0' then
Base_Adr(31 downto 24) <= DIN(31 downto 24);
end if;
end if;
end if;
end process ADRREG;
-- Address comparator
pADRCMP: process (FIRST_CYC,ACC_SPACE,DIN,Base_Adr)
begin
if (FIRST_CYC = '1') and (ACC_SPACE = '1') and Base_Adr(0)='1'and
(DIN(31 downto (32-EBAR_DWIDTH)) = Base_Adr(31 downto
(32-EBAR_DWIDTH))) then
Base_Hit <= '1';
else
Base_Hit <= '0';
end if;
end process pADRCMP;
-- BAR Size and Type Detection - all 1's detector
D_SIZE: Base_Size <= '1' when (Base_Adr = C_0xffffffff) else '0';
-- Tristate output buffer - valid bits
D_BUF1: DOUT(31 downto (32-EBAR_DWIDTH))<= Base_Adr (31 downto
(32-EBAR_DWIDTH)) when RD = '1'
else HI_Z_32(31 downto
(32-EBAR_DWIDTH));
-- Tristate output buffer - unused bits
D_BUF2: DOUT((31-EBAR_DWIDTH) downto 1)<= C_0x00000000((31-EBAR_DWIDTH)
downto 1) when RD = '1'
else HI_Z_32((31-EBAR_DWIDTH)
downto 1);
-- Tristate output buffer - bit 0 - ROM Enable
D_BUF3: DOUT(0) <= Base_Adr(0) when RD = '1' else 'Z';
-- Output Assignment
HIT <= Base_Hit when EBAR_PRESENT else '0';
SIZE <= Base_Size when EBAR_PRESENT else '1';
end RTL; -- EBAR
--
--*****************************************************************************
--* Interrupt Line Register
*
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_INTREG is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(7 downto 0); -- Data IN
DOUT : out std_logic_vector(7 downto 0); -- Data OUT
WE : in std_logic;
OE : in std_logic
);
end CFG_INTREG;
--
-- Interrupt Line Register RTL Architecture Desrciption
--
architecture RTL of CFG_INTREG is
signal IntLine : std_logic_vector(7 downto 0);
begin
-- Register
INTREG: process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
IntLine <= INTLINE_INIT;
elsif (CLK'event and CLK='1') then --CLK rising edge
if WE = '1' then
IntLine <= DIN;
end if;
end if;
end process;
-- Output Tristate Buffer
O_BUF: DOUT <= IntLine when OE='1' else "ZZZZZZZZ";
end RTL; -- CFG_INTREG
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