--*****************************************************************************
-- DESIGN  : PCI Target Application Template
-- FILE    : PCI_APP.vhd
-- DATE    : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr   : PCI Target application template for PCI Target Core
-- Entities: PCI_APP
-- Changes :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity PCI_APP is
   port (
      -- ************************ ATTENTION 
***********************************
      -- * Signals PRSNT[1:2] on PCI board must be tied to ground on the 
board*
      -- * to indicate that a board is physicaly present in motherboard.     
  *
      -- ************************ ATTENTION 
***********************************
      -- ## PCI Interface ## --
      RSTn_p     : in    std_logic;    -- Reset
      CLK_p      : in    std_logic;    -- Clock
      AD_p       : inout std_logic_vector(31 downto 0); -- Address/Data Bus
      CBE_p      : in std_logic_vector(3 downto 0);  -- Command/Byte Enable
      PAR_p      : inout std_logic;   -- Parity
      FRAMEn_p   : in std_logic;   -- Transaction Frame
      IRDYn_p    : in std_logic;   -- Initiator Ready
      TRDYn_p    : inout std_logic;   -- Target Ready
      DEVSELn_p  : inout std_logic;   -- Device Select
      STOPn_p    : inout std_logic;   -- Stop transaction
      IDSEL_p    : in    std_logic;   -- Chip Select
      PERRn_p    : inout std_logic;   -- Parity Error (s/t/s)
      SERRn_p    : inout std_logic;   -- System Error (o/d)
      INTAn_p    : inout std_logic    -- Interrupt pin (o/d)
      ----------------------------
      -- Add user I/O pins here --
      ----------------------------
   );
end PCI_APP;
--
--  PCI Target Core Architecture
--
architecture Struct of PCI_APP is
   -- Component declaration of the PCIT_CORE unit
   -- File name contains PCIMT_CORE entity: .\PCIT_CORE.vhd
   component PCI_T32
   port(
      RSTn_p : in std_logic;
      CLK_p : in std_logic;
      AD_p : inout std_logic_vector(31 downto 0);
      CBE_p : in std_logic_vector(3 downto 0);
      PAR_p : inout std_logic;
      FRAMEn_p : in std_logic;
      IRDYn_p : in std_logic;
      TRDYn_p : inout std_logic;
      DEVSELn_p : inout std_logic;
      STOPn_p : inout std_logic;
      IDSEL_p : in std_logic;
      PERRn_p : inout std_logic;
      SERRn_p : inout std_logic;
      INTAn_p : inout std_logic;
      APP_RST : out std_logic;
      APP_CLK : out std_logic;
      APP_ADR : out std_logic_vector(31 downto 0);
      APP_ADI : out std_logic_vector(31 downto 0);
      APP_ADO : in std_logic_vector(31 downto 0);
      APP_INTn : in std_logic;
      T_DRDY : in std_logic;
      T_ABORT : in std_logic;
      T_TERM : in std_logic;
      T_BARHIT : out std_logic_vector(5 downto 0);
      T_EBARHIT : out std_logic;
      T_BEn : out std_logic_vector(3 downto 0);
      T_CMD : out std_logic_vector(3 downto 0);
      T_RD : out std_logic;
      T_WR : out std_logic;
      T_WE : out std_logic;
      T_NEXTD : out std_logic;
      PCR_CMD : out std_logic_vector(15 downto 0);
      PCR_STAT : out std_logic_vector(15 downto 0)
      );
   end component;
   -- Component declaration of the USER_APP unit
   -- File name contains USER_APP entity: .\USER_APP.vhd
   component USER_APP
   port(
      APP_RST : in std_logic;
      APP_CLK : in std_logic;
      APP_ADR : in std_logic_vector(31 downto 0);
      APP_ADI : in std_logic_vector(31 downto 0);
      APP_ADO : out std_logic_vector(31 downto 0);
      APP_INTn : out std_logic;
      T_DRDY : out std_logic;
      T_ABORT : out std_logic;
      T_TERM : out std_logic;
      T_BARHIT : in std_logic_vector(5 downto 0);
      T_EBARHIT : in std_logic;
      T_BEn : in std_logic_vector(3 downto 0);
      T_CMD : in std_logic_vector(3 downto 0);
      T_RD : in std_logic;
      T_WR : in std_logic;
      T_WE : in std_logic;
      T_NEXTD : in std_logic;
      PCR_CMD : in std_logic_vector(15 downto 0);
      PCR_STAT : in std_logic_vector(15 downto 0)
      ----------------------------
      -- Add user I/O pins here --
      ----------------------------
      );
   end component;

   -- ## Application Interface Signals
   signal APP_RST : std_logic; -- RESET
   signal APP_CLK : std_logic; -- CLOCK
   signal APP_ADR : std_logic_vector(31 downto 0); -- Address Bus
   signal APP_ADI : std_logic_vector(31 downto 0); -- Data In (PCI =>> App)
   signal APP_ADO : std_logic_vector(31 downto 0); -- Data Out(App =>> PCI)
   signal APP_INTn : std_logic; -- Application Interrupt signal (Active 
Low!!)
   -- Target control signals
   signal T_DRDY : std_logic; -- Target Application Ready to Read/Write Data
   signal T_ABORT : std_logic; -- Target Abort Request
   signal T_TERM : std_logic; -- Target Termination Request 
(Retry/Disconnect)
   signal T_BARHIT : std_logic_vector(5 downto 0); -- BAR hit signal
   signal T_EBARHIT : std_logic; -- Expansion ROM BAR hit signal
   signal T_BEn : std_logic_vector(3 downto 0); -- Byte Enables (active low)
   signal T_CMD : std_logic_vector(3 downto 0); -- Command Code
   signal T_RD : std_logic; -- Target Operation is Read
   signal T_WR : std_logic; -- Target Operation is Write
   signal T_WE : std_logic; -- Target Write Enable
   signal T_NEXTD :  std_logic; -- Target Next Data
   -- Status Signals
   signal PCR_CMD : std_logic_vector(15 downto 0); -- Command Register 
Contens
   signal PCR_STAT : std_logic_vector(15 downto 0);  -- Status Register 
Contens
begin
  --
   -- PCI Target Interface Core Component
   --
   U0:PCI_T32 port map(
      RSTn_p      => RSTn_p,
      CLK_p       => CLK_p,
      AD_p        => AD_p,
      CBE_p       => CBE_p,
      PAR_p       => PAR_p,
      FRAMEn_p    => FRAMEn_p,
      IRDYn_p     => IRDYn_p,
      TRDYn_p     => TRDYn_p,
      DEVSELn_p   => DEVSELn_p,
      STOPn_p     => STOPn_p,
      IDSEL_p     => IDSEL_p,
      PERRn_p     => PERRn_p,
      SERRn_p     => SERRn_p,
      INTAn_p     => INTAn_p,
      APP_RST     => APP_RST,
      APP_CLK     => APP_CLK,
      APP_ADR     => APP_ADR,
      APP_ADI     => APP_ADI,
      APP_ADO     => APP_ADO,
      APP_INTn    => APP_INTn,
      T_DRDY      => T_DRDY,
      T_ABORT     => T_ABORT,
      T_TERM      => T_TERM,
      T_BARHIT    => T_BARHIT,
      T_EBARHIT   => T_EBARHIT,
      T_BEn       => T_BEn,
      T_CMD       => T_CMD,
      T_RD        => T_RD,
      T_WR        => T_WR,
      T_WE        => T_WE,
      T_NEXTD     => T_NEXTD,
      PCR_CMD     => PCR_CMD,
      PCR_STAT    => PCR_STAT
      );
   --
   -- User Application Component
   --
   U1: USER_APP port map(
      APP_RST     => APP_RST,
      APP_CLK     => APP_CLK,
      APP_ADR     => APP_ADR,
      APP_ADI     => APP_ADI,
      APP_ADO     => APP_ADO,
      APP_INTn    => APP_INTn,
      T_DRDY      => T_DRDY,
      T_ABORT     => T_ABORT,
      T_TERM      => T_TERM,
      T_BARHIT    => T_BARHIT,
      T_EBARHIT   => T_EBARHIT,
      T_BEn       => T_BEn,
      T_CMD       => T_CMD,
      T_RD        => T_RD,
      T_WR        => T_WR,
      T_WE        => T_WE,
      T_NEXTD     => T_NEXTD,
      PCR_STAT    => PCR_STAT,
      PCR_CMD     => PCR_CMD
    );
end Struct;