?? pcit_core.vhd
字號(hào):
--*****************************************************************************
-- DESIGN : PCI Target Core
-- FILE : PCIT_CORE.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Target Interface Core
-- Entities: PCI_T32
-- Changes :
-- 4.8.1999 - added visibility of Command and Status register bits
-- at the backend interface (PCR_CMD, PCR_STAT)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity PCI_T32 is
port (
-- ************************ ATTENTION
***********************************
-- * Signals PRSNT[1:2] on PCI board must be tied to ground on the
board*
-- * to indicate that a board is physicaly present in motherboard.
*
-- ************************ ATTENTION
***********************************
-- ## PCI Interface ## --
RSTn_p : in std_logic; -- Reset
CLK_p : in std_logic; -- Clock
AD_p : inout std_logic_vector(31 downto 0); -- Address/Data Bus
CBE_p : in std_logic_vector(3 downto 0); -- Command/Byte Enable
PAR_p : inout std_logic; -- Parity
FRAMEn_p : in std_logic; -- Transaction Frame
IRDYn_p : in std_logic; -- Initiator Ready
TRDYn_p : inout std_logic; -- Target Ready
DEVSELn_p : inout std_logic; -- Device Select
STOPn_p : inout std_logic; -- Stop transaction
IDSEL_p : in std_logic; -- Chip Select
PERRn_p : inout std_logic; -- Parity Error (s/t/s)
SERRn_p : inout std_logic; -- System Error (o/d)
INTAn_p : inout std_logic; -- Interrupt pin (o/d)
-- ## Application Interface Signals
APP_RST : out std_logic; -- RESET
APP_CLK : out std_logic; -- CLOCK
APP_ADR : out std_logic_vector(31 downto 0); -- Address Bus
APP_ADI : out std_logic_vector(31 downto 0); -- Data In (PCI =>>
App)
APP_ADO : in std_logic_vector(31 downto 0); -- Data Out(App =>>
PCI)
APP_INTn : in std_logic; -- Application Interrupt signal (Active
Low!!)
-- Target control signals
T_DRDY : in std_logic; -- Target Application Ready to Read/Write
Data
T_ABORT : in std_logic; -- Target Abort Request
T_TERM : in std_logic; -- Target Termination Request
(Retry/Disconnect)
T_BARHIT : out std_logic_vector(5 downto 0); -- BAR hit signal
T_EBARHIT : out std_logic; -- Expansion ROM BAR hit signal
T_BEn : out std_logic_vector(3 downto 0); -- Byte Enables
(active low)
T_CMD : out std_logic_vector(3 downto 0); -- Command Code
T_RD : out std_logic; -- Target Operation is Read
T_WR : out std_logic; -- Target Operation is Write
T_WE : out std_logic; -- Target Write Enable
T_NEXTD : out std_logic; -- Target Next Data
-- Status Signals
PCR_CMD : out std_logic_vector(15 downto 0); -- Command Register
Contens
PCR_STAT : out std_logic_vector(15 downto 0) -- Status Register
Contens
);
end PCI_T32;
--
-- PCI Target Core Architecture
--
architecture Struct of PCI_T32 is
-- Component declaration of the CHECK_PAR unit
-- File name contains CHECK_PAR entity: G_PARITY.vhd
component CHECK_PAR
port(
RESET : in std_logic;
CLK : in std_logic;
ADi : in std_logic_vector(31 downto 0);
BEn : in std_logic_vector(3 downto 0);
FIRST_CYC : in std_logic;
IRDYnid : in std_logic;
TRDYnid : in std_logic;
PARi : in std_logic;
PARid : in std_logic;
PERRni : in std_logic;
PERRnid : in std_logic;
SERRni : in std_logic;
SERRnid : in std_logic;
ACC_RD : in std_logic;
ACC_WR : in std_logic;
PERR_EN : in std_logic;
SERR_EN : in std_logic;
TARGET_ACT : in std_logic;
MASTER_READ : in std_logic;
MASTER_ACT : in std_logic;
NEW_PERRno : out std_logic;
NEW_SERRno : out std_logic;
NEW_OTPERR : out std_logic;
SET_MDPERR : out std_logic;
SIG_SERR : out std_logic;
DET_PERR : out std_logic);
end component;
component PCI_IO_Virtex
port(
RSTn_p : in std_logic;
CLK_p : in std_logic;
AD_p : inout std_logic_vector(31 downto 0);
CBE_p : in std_logic_vector(3 downto 0);
PAR_p : inout std_logic;
FRAMEn_p : in std_logic;
IRDYn_p : in std_logic;
TRDYn_p : inout std_logic;
DEVSELn_p : inout std_logic;
STOPn_p : inout std_logic;
IDSEL_p : in std_logic;
PERRn_p : inout std_logic;
SERRn_p : inout std_logic;
INTAn_p : inout std_logic;
RESET : out std_logic;
CLK : out std_logic;
ADi : out std_logic_vector(31 downto 0);
ADo : in std_logic_vector(31 downto 0);
CBEi : out std_logic_vector(3 downto 0);
CBEid : out std_logic_vector(3 downto 0);
PARi : out std_logic;
PARid : out std_logic;
PARo : in std_logic;
IDSELi : out std_logic;
FRAMEni : out std_logic;
IRDYni : out std_logic;
DEVSELni : out std_logic;
TRDYni : out std_logic;
STOPni : out std_logic;
IDSELid : out std_logic;
FRAMEnid : out std_logic;
IRDYnid : out std_logic;
DEVSELnid : out std_logic;
TRDYnid : out std_logic;
STOPnid : out std_logic;
NEW_DEVSELno: in std_logic;
NEW_TRDYno : in std_logic;
NEW_STOPno : in std_logic;
OT_DEVSEL : in std_logic;
OT_TRDY : in std_logic;
OT_STOP : in std_logic;
T_OT_AD : in std_logic;
CE_ADo : in std_logic;
T_CE_ADoRDY : in std_logic;
INTAno : in std_logic;
PERRni : out std_logic;
SERRni : out std_logic;
PERRnid : out std_logic;
SERRnid : out std_logic;
NEW_PERRno : in std_logic;
NEW_SERRno : in std_logic;
NEW_OTPERR : in std_logic);
end component PCI_IO_VIRTEX;
-- Command Register and Address Counter
component PCI_CMDADR is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(31 downto 0);
CBEnid : in std_logic_vector(3 downto 0);
IDSELd : in std_logic;
FRAMEnd : in std_logic;
ACC_END : in std_logic;
CFG_IOEN : in std_logic;
CFG_MEMEN : in std_logic;
INC_ADR : in std_logic;
FIRST_CYC : out std_logic;
ADR : out std_logic_vector(31 downto 0);
BURST_MODE : out std_logic_vector(1 downto 0);
COMMAND : out std_logic_vector(3 downto 0);
CMD_CFGRD : out std_logic;
CMD_IORD : out std_logic;
CMD_IOWR : out std_logic;
CMD_MRD : out std_logic;
CMD_MWR : out std_logic;
CMD_MRM : out std_logic;
CMD_MRL : out std_logic;
CMD_MWI : out std_logic;
ACC_CFG : out std_logic;
ACC_IO : out std_logic;
ACC_MEM : out std_logic;
ACC_WR : out std_logic;
ACC_RD : out std_logic);
end component PCI_CMDADR;
component CFG_SPACE is
port(
RESET : in std_logic; -- Chip Reset
CLK : in std_logic; -- Chip Clock
DIN : in std_logic_vector(31 downto 0);-- Data IN
DOUT : out std_logic_vector(31 downto 0);-- Data OUT
ADR : in std_logic_vector(7 downto 2); -- Register Address
BEn : in std_logic_vector(3 downto 0); -- Byte Enables
CMD_CFGRD : in std_logic; -- PCI Command Config.
Read
CMD_CFGWR : in std_logic; -- PCI Command Config.
Write
ACC_START : in std_logic; -- Start of Device
Access
ACC_END : in std_logic; -- End of Device Access
D_SENT : in std_logic; -- Data Sent
FIRST_CYC : in std_logic; -- First Cycle After FRAME#
falling edge
ACC_CFG : in std_logic; -- Configuration Space Access
ACC_IO : in std_logic; -- I/O Space Access
ACC_MEM : in std_logic; -- Memory Space Access
SET_MDPERR : in std_logic; -- Set Master Data Parity Error
Bit( 8)
SIG_TABORT : in std_logic; -- Set Signaled Target Abort Bit
(11)
RCV_TABORT : in std_logic; -- Set Received Target Abort Bit
(12)
RCV_MABORT : in std_logic; -- Set Received Master Abort Bit
(13)
SIG_SERR : in std_logic; -- Set Signaled System Error Bit
(14)
DET_PERR : in std_logic; -- Set Detected Parity Error Bit
(15)
DRDY : out std_logic; -- Ready to transfer data
CARD_HIT : out std_logic; -- Card was decoded as target
TARGET_ACT : out std_logic; -- Target Active
BAR_HIT : out std_logic_vector(5 downto 0); -- BAR Hit signal
ROM_HIT : out std_logic; -- Expansion ROM BAR Hit
PCR_CMD : out std_logic_vector(15 downto 0); -- Command Register
Contens
PCR_STAT : out std_logic_vector(15 downto 0); -- Status Register
Contens
IO_EN : out std_logic; -- I/O Space Decoding Enabled
MEM_EN : out std_logic; -- Memory Space Decoding Enabled
SPEC_CYC : out std_logic; -- Special Cycles Monitoring
Enabled
PERR_EN : out std_logic; -- Parity Error Response
STEPPING_EN : out std_logic; -- Stepping Control
SERR_EN : out std_logic); -- SERR# Enable
end component CFG_SPACE;
component TARGET_FSM is
port (
CLK : in std_logic;
RESET : in std_logic;
FRAMEni : in std_logic;
FRAMEnid : in std_logic;
IRDYni : in std_logic;
IRDYnid : in std_logic;
TRDYnid : in std_logic;
HIT : in std_logic;
DRDY : in std_logic;
TERM : in std_logic;
ABORT : in std_logic;
ACC_WR : in std_logic;
ACC_RD : in std_logic;
NEW_DEVSELno: out std_logic;
NEW_TRDYno : out std_logic;
NEW_STOPno : out std_logic;
CE_ADoDIR : out std_logic;
CE_ADoRDY : out std_logic;
NEW_OT_AD : out std_logic;
OT_TRDYn : out std_logic;
OT_STOPn : out std_logic;
OT_DEVSELn : out std_logic;
ACC_START : out std_logic;
ACC_END : out std_logic;
D_SENT : out std_logic;
INC_ADR : out std_logic;
T_NEXTD : out std_logic;
T_WE : out std_logic;
T_WR : out std_logic;
T_RD : out std_logic
);
end component TARGET_FSM;
--
-- Local Signals
signal RESET : std_logic; -- Chip Reset
signal CLK : std_logic; -- Chip Clock
signal ADo : std_logic_vector(31 downto 0); -- Address/Data Bus
signal ADi : std_logic_vector(31 downto 0); -- Address/Data Bus
signal T_OT_AD : std_logic; -- Target DATA Output Tristate control
signal M_OT_AD : std_logic; -- Master DATA Output Tristate control
signal CBEi : std_logic_vector(3 downto 0);-- Command/Byte Enable
signal CBEid : std_logic_vector(3 downto 0);-- Command/Byte Enable
signal PARi : std_logic; -- Parity In (-> Board)
signal PARo : std_logic; -- Parity Out (Board ->)
-- Direct PCI Inputs
signal IDSELi : std_logic;
signal FRAMEni : std_logic;
signal IRDYni : std_logic;
signal TRDYni : std_logic;
signal STOPni : std_logic;
-- Registered PCI Inputs
signal IDSELid : std_logic;
signal FRAMEnid : std_logic;
signal IRDYnid : std_logic;
signal DEVSELnid : std_logic;
signal TRDYnid : std_logic;
signal STOPnid : std_logic;
-- Direct PCI Outputs
signal NEW_FRAMEno : std_logic;
signal NEW_IRDYno : std_logic;
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