?? pcit_core.vhd
字號:
signal NEW_DEVSELno : std_logic;
signal NEW_TRDYno : std_logic;
signal NEW_STOPno : std_logic;
-- Tristate buffer control
signal OT_FRAME : std_logic; -- PCI FRAME# signal buffers enable
signal OT_IRDY : std_logic; -- PCI IRDY# signal buffers enable
signal CE_OT_IRDY : std_logic;
signal NEW_OT_IRDY : std_logic;
signal OT_DEVSEL : std_logic; -- DEVSEL# Buffer Control
signal OT_TRDY : std_logic; -- TRDY# Buffer Control
signal OT_STOP : std_logic; -- STOP# Buffer Control
signal NEW_OT_CBE : std_logic; -- PCI C/BE#[3:0] signal buffers enable
signal REQn : std_logic; -- Bus Mastering Request
signal GNTni : std_logic; -- Bus Mastering Grant
signal GNTnid : std_logic; -- Bus Mastering Grant
signal PERRni : std_logic; -- Parity Error In
signal SERRni : std_logic; -- System Error In
signal NEW_PERRno : std_logic; -- Parity Error Out
signal NEW_SERRno : std_logic; -- System Error Out
signal NEW_OTPERR : std_logic; -- Parity Error Buffer Control
signal CE_ADo : std_logic;
signal INC_ADR : std_logic;
--
signal FIRST_CYC : std_logic; -- First Cycle After FRAME# falling edge
signal ADR : std_logic_vector(31 downto 0);
signal BURST_MODE : std_logic_vector(1 downto 0);
signal COMMAND : std_logic_vector(3 downto 0); -- Binary encoded command
signal CMD_CFGRD : std_logic; -- Configuration Read
signal CMD_CFGWR : std_logic; -- Configuration Write
signal CMD_IORD : std_logic; -- I/O Read
signal CMD_IOWR : std_logic; -- I/O Write
signal CMD_MRD : std_logic; -- Memory Read
signal CMD_MWR : std_logic; -- Memory Write
signal CMD_MRM : std_logic; -- Memory Read Multiple
signal CMD_MRL : std_logic; -- Memory Read Line
signal CMD_MWI : std_logic; -- Memory Write and Invalidate
signal ACC_CFG : std_logic; -- Configuration Space Access
signal ACC_IO : std_logic; -- I/O Space Access
signal ACC_MEM : std_logic; -- Memory Space Access
signal ACC_WR : std_logic; -- Card Write Access
signal ACC_RD : std_logic; -- Card Read Access
-- Config Space Inputs
signal SET_MDPERR : std_logic; -- Set Master Data Parity Error Bit( 8)
-- signal SIG_TABORT : std_logic; -- Set Signaled Target Abort Bit (11)
-- signal RCV_TABORT : std_logic; -- Set Received Target Abort Bit (12)
-- signal RCV_MABORT : std_logic;-- Set Received Master Abort Bit (13)
signal SIG_SERR : std_logic;-- Set Signaled System Error Bit (14)
signal DET_PERR : std_logic;-- Set Detected Parity Error Bit (15)
-- Config Space Outputs
signal DRDY_CFG: std_logic;
signal CARD_HIT: std_logic; -- Card was decoded as target
signal IO_EN : std_logic; -- I/O Space Decoding Enabled
signal MEM_EN : std_logic; -- Memory Space Decoding Enabled
signal MASTER_EN : std_logic; -- Bus Master Enabled
signal SPEC_CYC : std_logic; -- Special Cycles Monitoring Enabled
signal MWI_EN : std_logic; -- Memory Write and Invalidate Enabled
signal PERR_EN : std_logic; -- Parity Error Response
signal STEPPING_EN : std_logic; -- Stepping Control
signal SERR_EN : std_logic; -- SERR# Enable
signal LAT_TIMER : std_logic_vector(7 downto 0); -- Latency Timer
register
signal CACHE_SIZE : std_logic_vector(7 downto 0); -- Cache Line Size
register
signal TARGET_ACT : std_logic;
-- Signals Driven by TARGET_FSM
signal ACC_START : std_logic; -- Start of Device Access
signal ACC_END : std_logic; -- End of Device Access
signal D_SENT : std_logic; -- Data Sent
signal T_CE_ADoDIR : std_logic;
signal T_CE_ADoRDY : std_logic;
signal M_CEADO : std_logic;
-- Signals to control TARGET_FSM
signal DRDY_Sys : std_logic; -- Ready to transfer data
-- Master FSM signals
signal MABORT_SIG: std_logic;
signal TABORT_DET: std_logic;
signal TRETRY_DET : std_logic;
signal TDISC_DET : std_logic;
--
signal MASTER_ACT: std_logic;
signal PARid:std_logic;
signal SERRnid,PERRnid: std_logic;
signal LT_WE : std_logic;
signal Log0: std_logic;
begin
Log0 <= '0';
-- Application signals assignment
APP_RST <= RESET; -- Application reset
APP_CLK <= CLK; -- Application clock
APP_ADR <= ADR; -- Application Address bus assignment
APP_ADi <= ADi; -- Application Data In bus assignment
ADo <= APP_ADO; -- Application Data Out bus assignment
T_BEn <= CBEid; -- Target Byte Enables
T_CMD <= COMMAND; -- Target Command
T_WE <= LT_WE; --Target Write Enable assignment
--
U1: CHECK_PAR port map(
RESET => RESET,
CLK => CLK,
ADi => ADi,
BEn => CBEid,
FIRST_CYC => FIRST_CYC,
IRDYnid => IRDYnid,
TRDYnid => TRDYnid,
PARi => PARi,
PARid => PARid,
PERRni => PERRni,
PERRnid => PERRnid,
SERRni => SERRni,
SERRnid => SERRnid,
ACC_RD => ACC_RD,
ACC_WR => ACC_WR,
PERR_EN => PERR_EN, -- PERR# enabled
SERR_EN => SERR_EN, -- SERR# enabled
TARGET_ACT => TARGET_ACT, -- Target Active
MASTER_ACT => Log0, -- Master Active
MASTER_READ => Log0, -- Master performs read operation
NEW_PERRno => NEW_PERRno, -- PERR# output
NEW_SERRno => NEW_SERRno,
NEW_OTPERR => NEW_OTPERR,
SET_MDPERR => SET_MDPERR,
DET_PERR => DET_PERR, -- Parity Error Detected
SIG_SERR => SIG_SERR -- System Error signaled
);
--
CE_ADo <= T_CE_ADoDIR;
--
U2: PCI_IO_Virtex port map(
-- PCI Signals
RSTn_p => RSTn_p, -- Reset
CLK_p => CLK_p, -- Clock
AD_p => AD_p, -- Address/Data Bus
CBE_p => CBE_p, -- Command/Byte Enable
PAR_p => PAR_p, -- Parity
FRAMEn_p => FRAMEn_p, -- Transaction Frame
IRDYn_p => IRDYn_p, -- Initiator Ready
TRDYn_p => TRDYn_p, -- Target Ready
DEVSELn_p => DEVSELn_p, -- Device Select
STOPn_p => STOPn_p, -- Stop transaction
IDSEL_p => IDSEL_p, -- Chip Select
PERRn_p => PERRn_p, -- Parity Error (s/t/s)
SERRn_p => SERRn_p, -- System Error (o/d)
INTAn_p => INTAn_p, -- Interrupt pin (o/d)
-- Local Signals
RESET => RESET, -- Chip Reset
CLK => CLK, -- Chip Clock
ADo => ADo, -- Address/Data Bus
ADi => ADi, -- Address/Data Bus
CBEi => CBEi,
CBEid => CBEid, -- Command/Byte Enable
PARo => PARo, -- Parity Out (Board ->)
PARi => PARi, -- Parity In (-> Board)
PARid => PARid,
-- Direct PCI Inputs
IDSELi => IDSELi,
FRAMEni => FRAMEni,
IRDYni => IRDYni,
DEVSELni => DEVSELni,
TRDYni => TRDYni,
STOPni => STOPni,
-- Registered PCI Inputs
IDSELid => IDSELid,
FRAMEnid => FRAMEnid,
IRDYnid => IRDYnid,
DEVSELnid => DEVSELnid,
TRDYnid => TRDYnid,
STOPnid => STOPnid,
-- Direct PCI Outputs
NEW_DEVSELno=> NEW_DEVSELno,
NEW_TRDYno => NEW_TRDYno,
NEW_STOPno => NEW_STOPno,
-- Tristate buffer control
OT_DEVSEL => OT_DEVSEL, -- DEVSEL# Buffer Control
OT_TRDY => OT_TRDY, -- TRDY# Buffer Control
OT_STOP => OT_STOP, -- STOP# Buffer Control
T_OT_AD => T_OT_AD, -- Target DATA Output Tristate control
CE_ADo => CE_ADo,
T_CE_ADoRDY => T_CE_ADoRDY,
-- Bus Arbitration and Interrupts
INTAno => APP_INTn, -- Interrupt
-- Error reporting signals
PERRni => PERRni, -- Parity Error In Direct
SERRni => SERRni, -- System Error In Direct
PERRnid => PERRnid, -- Parity Error In Registered
SERRnid => SERRnid, -- System Error In Registered
NEW_PERRno => NEW_PERRno, -- PERR# output
NEW_SERRno => NEW_SERRno,
NEW_OTPERR => NEW_OTPERR
); -- end component PCI_IO_Virtex;
--
U3: PCI_CMDADR port map(
RESET => RESET, -- Chip Reset
CLK => CLK, -- Chip Clock
DIN => ADi, -- Address/Data Bus
CBEnid => CBEid, -- Command/Byte Enable
IDSELd => IDSELid, -- Clocked Chip Select
FRAMEnd => FRAMEnid, -- Clocked Transaction Frame
ACC_END => ACC_END,
CFG_IOEN => IO_EN, -- I/O Space Decoding Enabled
CFG_MEMEN => MEM_EN, -- Memory Space Decoding Enabled
INC_ADR => INC_ADR, -- Incement Address Counter
FIRST_CYC => FIRST_CYC, -- First Cycle After FRAME# falling
edge
ADR => ADR, -- Captured address
BURST_MODE => BURST_MODE, --
COMMAND => COMMAND, -- Binary encoded command
CMD_CFGRD => CMD_CFGRD, -- Configuration Read
CMD_CFGWR => CMD_CFGWR, -- Configuration Write
CMD_IORD => CMD_IORD, -- I/O Read
CMD_IOWR => CMD_IOWR, -- I/O Write
CMD_MRD => CMD_MRD, -- Memory Read
CMD_MWR => CMD_MWR, -- Memory Write
CMD_MRM => CMD_MRM, -- Memory Read Multiple
CMD_MRL => CMD_MRL, -- Memory Read Line
CMD_MWI => CMD_MWI, -- Memory Write and Invalidate
ACC_CFG => ACC_CFG, -- Configuration Space Access
ACC_IO => ACC_IO, -- I/O Space Access
ACC_MEM => ACC_MEM, -- Memory Space Access
ACC_WR => ACC_WR, -- Card Write Access
ACC_RD => ACC_RD -- Card Read Access
); -- end component PCI_CMDADR;
--
-- PCI Configuration Space Entity
--
U4: CFG_SPACE port map(
RESET => RESET, -- Chip Reset
CLK => CLK, -- Chip Clock
DIN => ADi, -- Data In Bus
DOUT => ADo, -- Data Out Bus
ADR => ADR(7 downto 2), -- Address Bus
BEn => CBEid, -- Byte Enables
CMD_CFGRD => CMD_CFGRD, -- Configuration Read Command
CMD_CFGWR => CMD_CFGWR, -- Configuration Write Command
ACC_START => ACC_START, -- Start of Device Access
ACC_END => ACC_END, -- End of Device Access
D_SENT => D_SENT, -- Data Sent
FIRST_CYC => FIRST_CYC, -- First Cycle After FRAME#
falling edge
ACC_CFG => ACC_CFG, -- Configuration Space Access
ACC_IO => ACC_IO, -- I/O Space Access
ACC_MEM => ACC_MEM, -- Memory Space Access
SET_MDPERR => SET_MDPERR, -- Set Master Data Parity Error
Bit( 8)
SIG_TABORT => T_ABORT, -- Set Signaled Target Abort Bit
RCV_TABORT => TABORT_DET, -- Set Received Target Abort Bit
(12)
RCV_MABORT => MABORT_SIG, -- Set Received Master Abort Bit
(13)
SIG_SERR => SIG_SERR, -- Set Signaled System Error Bit
(14)
DET_PERR => DET_PERR, -- Set Detected Parity Error Bit
(15)
DRDY => DRDY_CFG, -- CFG Space Ready to transfer
data
PCR_CMD => PCR_CMD, -- Command Register Contens
PCR_STAT => PCR_STAT, -- Status Register Contens
CARD_HIT => CARD_HIT,
TARGET_ACT => TARGET_ACT,
BAR_HIT => T_BARHIT,
ROM_HIT => T_EBARHIT,
IO_EN => IO_EN,
MEM_EN => MEM_EN,
SPEC_CYC => SPEC_CYC,
PERR_EN => PERR_EN,
STEPPING_EN => STEPPING_EN,
SERR_EN => SERR_EN
); -- end component CFG_SPACE;
--
-- DRDY Signal assignment
--
GL1: DRDY_Sys <= DRDY_CFG or T_DRDY;
--
-- Target FSM Component
--
U5: TARGET_FSM port map(
RESET => RESET, -- Chip Reset
CLK => CLK, -- Chip Clock
FRAMEni => FRAMEni, -- PCI Frame#
FRAMEnid => FRAMEnid, -- PCI Frame#
IRDYni => IRDYni, -- PCI Irdy#
IRDYnid => IRDYnid, -- PCI Irdy# registered by FF
TRDYnid => TRDYnid, -- PCI Trdy# registered by FF
HIT => CARD_HIT, -- Hit on address decode
DRDY => DRDY_Sys, -- Ready to transfer data
TERM => T_TERM, -- Terminate transaction
ABORT => T_ABORT, -- Target error - abort transaction
ACC_WR => ACC_WR, -- Command is Write
ACC_RD => ACC_RD, -- Command is Read
NEW_DEVSELno=> NEW_DEVSELno, -- PCI Devsel#
NEW_STOPno => NEW_STOPno, -- PCI Stop#
NEW_TRDYno => NEW_TRDYno, -- PCI Trdy#
CE_ADoDIR => T_CE_ADoDIR, -- Clock Enable of Output FFs -
direct
CE_ADoRDY => T_CE_ADoRDY, -- Clock Enable of Output FFs - ready
for next transfer
NEW_OT_AD => T_OT_AD, -- PCI AD bus enable
OT_TRDYn => OT_TRDY, -- PCI Trdy# enable
OT_STOPn => OT_STOP, -- PCI Stop# enable
OT_DEVSELn => OT_DEVSEL, -- PCI Devsel# enable
ACC_START => ACC_START, -- Start of Device Access
ACC_END => ACC_END, -- End of Device Access
D_SENT => D_SENT, -- Data Sent
INC_ADR => INC_ADR, -- Address Counter Increment
T_NEXTD => T_NEXTD, -- Target ready to process NEXT Data
T_WE => LT_WE, -- Target Data Write Enable
T_WR => T_WR, -- Target Write in progress
T_RD => T_RD -- Target Read in progress
); -- end component TARGET_FSM;
end Struct; -- PCIT_CORE
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