################################################################################# Actual Synthesis Script## This script does the actual synthesis## Author: Rudolf Usselmann#         rudi@asics.ws## Revision:# 3/7/01 RU Initial Sript################################################################################## ==============================================# Setup Design Parameterssource ../bin/design_spec.dc# ==============================================# Setup Librariessource ../bin/lib_spec.dc# ==============================================# Setup File IOset junk_file /dev/nullappend log_file              ../log/$active_design "_cmp.log"append pre_comp_db_file      ../out/$design_name   "_pre.db"append post_comp_db_file     ../out/$design_name   ".db"append post_syn_verilog_file ../out/$design_name   "_ps.v"sh rm -f $log_file# ==============================================# Setup Misc Variablesset hdlin_enable_vpp true       ;# Important - this enables 'ifdefs# Turn off automatic wire load selection, as this always (WHY ???) defaults to "zero_load"#set auto_wire_load_selection false# ==============================================# Read Designecho "+++++++++ Reading Design ..."                             >> $log_fileread_file $pre_comp_db_file                                     >> $log_file# ==============================================# Operating conditionsecho "+++++++++ Setting up Operation Conditions ..."            >> $log_filecurrent_design $design_nameset_operating_conditions WORST                                  >> $log_file#set_wire_load_mode enclosed                                    >> $log_fileset_wire_load_mode top                                          >> $log_fileset_wire_load_model -name suggested_40K                         >> $log_file# ==============================================# Setup Clocks and Resetsecho "+++++++++ Setting up Clocks ..."                          >> $log_fileset_drive 0 [find port {*clk_i}]# !!! Phy Clock !!!set clock_period2 16create_clock -period $clock_period2 phy_clkset_clock_skew -uncertainty 0.5 phy_clkset_clock_transition 0.9 phy_clkset_dont_touch_network phy_clk# !!! WISHBONE Clock !!!set clock_period 5create_clock -period $clock_period clk_iset_clock_skew -uncertainty 0.1 clk_iset_clock_transition 0.5 clk_iset_dont_touch_network clk_i# !!! Reset !!!set_drive 0 [find port {rst*}]set_dont_touch_network [find port {rst*}]# ==============================================# Setup IOsecho "+++++++++ Setting up IOs ..."                             >> $log_file# Need to spell out external IOsset_driving_cell -cell NAND2D2 -pin Z [all_inputs]              >> $junk_fileset_load 0.2 [all_outputs]set_input_delay -max 1 -clock clk_i [all_inputs]set_output_delay -max 1 -clock clk_i [all_outputs]set_input_delay -max 1 -clock phy_clk [all_inputs]set_output_delay -max 1 -clock phy_clk [all_outputs]# ==============================================# Setup Area Constrainsset_max_area 0.0# ==============================================# Force Ultraset_ultra_optimization -f# ==============================================# Compile Designecho "+++++++++ Starting Compile ..."                           >> $log_file#compile -map_effort medium -area_effort medium -ungroup_all    >> $log_filecompile -map_effort low -area_effort low                        >> $log_file#compile -map_effort high -area_effort high -auto_ungroup        >> $log_file# ==============================================# Write Out the optimized designecho "+++++++++ Saving Optimized Design ..."                    >> $log_filewrite_file -format verilog -output $post_syn_verilog_filewrite_file -hierarchy -format db -output $post_comp_db_file# ==============================================# Create Some Basic Reportsecho "+++++++++ Reporting Final Results ..."                    >> $log_filereport_timing -nworst 10                                        >> $log_filereport_area                                                     >> $log_file